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參數資料
型號: MC74F162A
廠商: Motorola, Inc.
元件分類: 通用總線功能
英文描述: SYNCHRONOUS PRESETTABLE BCD DECADE COUNTER
中文描述: 同步可預置BCD碼十進制計數器
文件頁數: 3/4頁
文件大小: 86K
代理商: MC74F162A
4-73
FAST AND LS TTL DATA
MC74F160A
MC74F162A
GUARANTEED OPERATING RANGES
Symbol
Parameter
Min
Typ
Max
Unit
VCC
Supply Voltage
74
4.5
5.0
5.5
V
TA
Operating Ambient Temperature Range
74
0
25
70
°
C
IOH
Output Current — High
74
–1.0
mA
IOL
Output Current — Low
74
20
mA
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE
(unless otherwise specified)
Limits
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
VIH
Input HIGH Voltage
2.0
V
Guaranteed Input HIGH Voltage for
All Inputs
VIL
Input LOW Voltage
0.8
V
Guaranteed Input LOW Voltage for
All Inputs
VIK
Input Clamp Diode Voltage
–1.2
V
VCC = MIN, IIN = – 18 mA
VOH
Output HIGH Voltage
74
2.5
3.4
V
IOH = –1.0 mA
VCC = 4.50 V
74
2.7
3.4
V
IOH = –1.0 mA
VCC = 4.75 V
VOL
Output LOW Voltage
0.35
0.5
V
IOL = 20 mA
VCC = MIN
IIH
Input HIGH Current
20
μ
A
VCC = MAX, VIN = 2.7 V
0.1
mA
VCC = MAX, VIN = 7.0 V
IIL
Input LOW Current
MR, Data, CEP, Clock
PE, CET, SR
–0.6
–1.2
mA
VCC = MAX, VIN = 0.5 V
IOS
Output Short Circuit Current (Note 2)
–60
– 150
mA
VCC = MAX, VOUT = 0 V
ICC
Power Supply Current
37
55
mA
VCC = MAX
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable device type.
2. Not more than one output should be shorted at a time, nor for more than 1 second.
The Terminal Count (TC) output is HIGH when CET is HIGH
and the counter is in state 9. To implement synchronous multi-
stage counters, the TC outputs can be used with the CEP and
CET inputs in two different ways. Please refer to the
MC74F568 data sheet. The TC output is subject to decoding
spikes due to internal race conditions and is therefore not rec-
ommended for use as a clock or asynchronous reset for
flip-flops, counters, or registers. In the MC74F160A and
MC74F162A decade counters, the TC output is fully decoded
and can only be HIGH in state 9. If a decade counter is preset
to an illegal state, or assumes an illegal state when power is
applied, it will return to the normal sequence within two
counts, as shown in the State Diagram.
Logic Equations:
Count Enable = CEP
CET
PE
TC = Q0
Q1
Q2
Q3
CET
相關PDF資料
PDF描述
MC74F162AD SYNCHRONOUS PRESETTABLE BCD DECADE COUNTER
MC74F162AJ SYNCHRONOUS PRESETTABLE BCD DECADE COUNTER
MC74F162AN SYNCHRONOUS PRESETTABLE BCD DECADE COUNTER
MC74F160AJ Processor Supervisory Circuits 5-SOT-23 -40 to 85
MC74F160AN Processor Supervisory Circuits 5-SOT-23 -40 to 85
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