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參數(shù)資料
| 型號： | MC74F256N |
| 廠商： | MOTOROLA INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | Processor Supervisory Circuits 5-SOT-23 -40 to 85 |
| 中文描述： | F/FAST SERIES, LOW LEVEL TRIGGERED D LATCH, TRUE OUTPUT, PDIP16 |
| 封裝： | 648-08 |
| 文件頁數(shù)： | 1/4頁 |
| 文件大小： | 112K |
| 代理商： | MC74F256N |
4-123
FAST AND LS TTL DATA
DUAL 4-BIT
ADDRESSABLE LATCH
The MC54/74F256 dual addressable latch has four distinct modes of opera-
tion which are selectable by controlling the Clear and Enable inputs (see
Function Table). In the addressable latch mode, data at the Data (D) inputs
is written into the addressed latches. The addressed latches will follow the
Data input with all unaddressed latches remaining in their previous states.
In the memory mode, all latches remain in their previous states and are un-
affected by the Data or Address inputs. To eliminate the possibility of entering
erroneous data in the latches, the enable should be held HIGH (inactive) while
the address lines are changing. In the dual 1-of-4 decoding or demultiplexing
mode (MR = E = LOW), addressed outputs will follow the level of the D inputs
with all other outputs LOW. In the clear mode, all outputs are LOW and unef-
fected by the Address and Data inputs.
Combines Dual Demultiplexer and 8-Bit Latch
Serial-to-Parallel Capability
Output from Each Storage Bit Available
Random (Addressable) Data Entry
Easily Expandable
Common Clear Input
Useful as Dual 1-of-4 Active HIGH Decoder
CONNECTION DIAGRAM
14
13
12
11
10
9
1
2
3
4
5
6
7
16
15
8
VCC
A0
MR
E
Db
Q3b
Q1b
Q2b
Q0b
A1
Da
Q0a
Q1a
Q2a
Q3a
GND
FUNCTION TABLE
Inputs
Outputs
Operating Mode
MR
E
D
A0
A1
Q0
Q1
Q2
Q3
Master Reset
L
H
X
X
X
L
L
L
L
D = H)
L
L
L
L
L
L
L
L
d
d
d
d
L
H
L
H
L
L
H
H
Q=d
L
L
L
L
L
L
L
L
L
Demultiplex (Active
HIGH Decoder when
Q=d
L
L
Q=d
L
Q=d
Store (Do Nothing)
H
H
X
X
X
q0
q1
q2
q3
Latch
H
H
H
H
L
L
L
L
d
d
d
d
L
H
L
H
L
L
H
H
Q=d
q0
q0
q0
q1
Q=d
q1
q1
q2
q2
Q=d
q2
q3
q3
q3
Q=d
Addressable
H = HIGH Voltage Level Steady State
L = LOW Voltage Level Steady State
X = Immaterial
d = HIGH or LOW Data one setup time prior to the LOW-to-HIGH Enable transition.
q = Lower case letters indicate the state of the referenced output established during the last cycle
in which it was addressed or cleared.
MC54/74F256
DUAL 4-BIT
ADDRESSABLE LATCH
J SUFFIX
CERAMIC
CASE 620-09
N SUFFIX
PLASTIC
CASE 648-08
16
1
16
1
ORDERING INFORMATION
MC54FXXXJ
MC74FXXXN
MC74FXXXD
Ceramic
Plastic
SOIC
16
1
D SUFFIX
SOIC
CASE 751B-03
LOGIC SYMBOL
3
Da
Db
E
MR
A0
A1
Q0aQ1aQ2aQ3aQ0bQ1bQ2bQ3b
FAST
SCHOTTKY TTL
13
1
2
14
15
4
5
6
7
9
10
11
12
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC74F257 MOT 92 | 制造商:Motorola 功能描述:74F257N |
| MC74F257A WAF | 制造商:ON Semiconductor 功能描述: |
| MC74F257AD | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MC74F257ADR2 | 制造商:Motorola Inc 功能描述: |
| MC74F257AM | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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