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參數(shù)資料
型號: MC74HC03ADT
廠商: ON SEMICONDUCTOR
元件分類: 通用總線功能
英文描述: Quad 2-Input NAND Gate with Open-Drain Outputs
中文描述: HC/UH SERIES, QUAD 2-INPUT NAND GATE, PDSO14
封裝: TSSOP-14
文件頁數(shù): 2/7頁
文件大小: 175K
代理商: MC74HC03ADT
MOTOROLA
High–Speed CMOS Logic Data
DL129 — Rev 6
2
SOIC Package
TSSOP Package
Tstg
TL
Storage Temperature
500
450
– 65 to + 150
C
Lead Temperature, 1 mm from Case for 10 Seconds
C
Functional operation should be restricted to the Recommended Operating Conditions.
Derating — Plastic DIP: – 10 mW/ C from 65 to 125 C
SOIC Package: – 7 mW/ C from 65 to 125 C
TSSOP Package: – 6.1 mW/ C from 65 to 125 C
0
400
VCC = 6.0 V
V
Guaranteed Limit
–55 to 25
°
C
Symbol
Parameter
Condition
VCC
85
°
C
125
°
C
Unit
VIH
Minimum High–Level Input Voltage
Vout = 0.1V or VCC –0.1V
|Iout|
20
μ
A
2.0
3.0
4.5
6.0
1.50
2.10
3.15
4.20
1.50
2.10
3.15
4.20
1.50
2.10
3.15
4.20
V
VIL
Maximum Low–Level Input Voltage
Vout = 0.1V or VCC – 0.1V
|Iout|
20
μ
A
2.0
3.0
4.5
6.0
0.50
0.90
1.35
1.80
0.50
0.90
1.35
1.80
0.50
0.90
1.35
1.80
V
VOL
Maximum Low–Level Output
Voltage
Vout = 0.1V or VCC – 0.1V
|Iout|
20
μ
A
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
Vin = VIH or VIL
|Iout|
2.4mA
|Iout|
4.0mA
|Iout|
5.2mA
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.40
0.40
0.40
Iin
ICC
Maximum Input Leakage Current
Vin = VCC or GND
Vin = VCC or GND
Iout = 0
μ
A
6.0
±
0.1
±
1.0
±
1.0
μ
A
Maximum Quiescent Supply
Current (per Package)
6.0
1.0
10
40
μ
A
IOZ
Maximum Three–State Leakage
Current
Output in High–Impedance State
Vin = VIL or VIH
Vout = VCC or GND
6.0
±
0.5
±
5.0
±
10
μ
A
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance cir-
cuit. For proper operation, Vin and
Vout should be constrained to the
range GND (Vin or Vout)
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
VCC.
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