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參數資料
| 型號： | MC74HC160N |
| 廠商： | MOTOROLA INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | Presettable Counters |
| 中文描述： | HC/UH SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP DECADE COUNTER, PDIP16 |
| 封裝： | PLASTIC, DIP-16 |
| 文件頁數： | 3/13頁 |
| 文件大小： | 338K |
| 代理商： | MC74HC160N |
MC54/74HC160 MC54/74HC162
High–Speed CMOS Logic Data
DL129 — Rev 6
3
MOTOROLA
(Figures 1 and 7)
4.5
30
20
6.0
29
24
43
tPHL
2.0
205
255
37
310
(Figures 2 and 7)
4.5
42
63
6.0
27
53
41
tPHL
2.0
6.0
195
33
245
34
295
50
Maximum Propagation Delay, Clock to Ripple Carry Out
(Figures 1 and 7)
2.0
4.5
175
35
220
42
265
53
ns
4.5
6.0
43
37
44
65
55
tPHL
Maximum Propagation Delay, Reset to Ripple Carry Out
(Figures 2 and 7)
2.0
6.0
220
37
275
54
46
330
56
ns
tTHL
Maximum Output Transition Time, Any Output
(Figures 1 and 7)
2.0
4.5
75
15
47
110
22
ns
propagation delays, (2) Enable T or Enable P to Clock setup times, and (3) Clock to Enable T or Enable P hold times determine fmax. However,
if Ripple Carry Out of each stage is tied to the Clock of the next stage (nonsynchronously clocked), the fmax in the table above is applicable.
See Applications Information in this data sheet.
NOTES:
1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
2. Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
95
19
CPD
Power Dissipation Capacitance (Per Package)*
* Used to determine the no–load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the
Motorola High–Speed CMOS Data Book (DL129/D).
Typical @ 25
°
C, VCC = 5.0 V
60
pF
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