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參數資料
| 型號： | MC74HC299N |
| 廠商： | MOTOROLA INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | TIE WING PUSH MOUNT STD NAT 7.8,1 |
| 中文描述： | HC/UH SERIES, 8-BIT BIDIRECTIONAL PARALLEL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDIP20 |
| 封裝： | PLASTIC, DIP-20 |
| 文件頁數： | 2/8頁 |
| 文件大小： | 268K |
| 代理商： | MC74HC299N |
MOTOROLA
High–Speed CMOS Logic Data
DL129 — Rev 6
3–2
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
Iout
DC Output Current, per Pin
ICC
DC Supply Current, VCC and GND Pins
PD
Power Dissipation in Still Air
±
20
±
35
±
75
Plastic DIP
V
mA
mA
mA
750
mW
(Plastic DIP or SOIC Package)
260
* Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
Derating — Plastic DIP: – 10 mW/ C from 65 to 125 C
SOIC Package: – 7 mW/ C from 65 to 125 C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Vin, Vout
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Min
2.0
0
Max
6.0
VCC
Unit
V
V
0
400
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
VCC = 6.0 V
VIH
2.0
2.0
2.0
6.0
2.0
4.5
6.0
6.0
6.0
Guaranteed Limit
1.5
0.3
1.9
5.48
5.34
0.1
0.26
0.26
0.33
±
0.1
±
1.0
±
0.5
±
5.0
V
Minimum High–Level Input
Vout = 0.1 V or VCC – 0.1 V
1.5
1.5
0.3
1.9
5.20
0.1
0.40
0.40
±
1.0
±
10
Maximum Low–Level Input
0.3
Minimum High–Level Output
1.9
V
|Iout|
Vin = VIH or VIL
V
7.8 mA (P/Q)
Maximum Low–Level Output
0.1
Vin = VCC or GND
Output in High–Impedance State
Vout = VCC or GND
Vin = VCC or GND
0.33
V
6.0 mA (P/Q)
5.2 mA (Q
)
Iin
IOZ
Maximum Input Leakage Current
Maximum Three–State Leakage
μ
A
μ
A
ICC
Maximum Quiescent Supply
6.0
8
80
160
μ
A
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance cir-
cuit. For proper operation, Vin and
Vout should be constrained to the
range GND (Vin or Vout)
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
I/O pins must be connected to a
properly terminated line or bus.
VCC.
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