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參數資料
| 型號： | MC74HC4020AD |
| 廠商： | MOTOROLA INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | 14-Stage Binary Ripple Counter |
| 中文描述： | HC/UH SERIES, ASYN NEGATIVE EDGE TRIGGERED 14-BIT UP BINARY COUNTER, PDSO16 |
| 封裝： | 0.150 INCH, PLASTIC, SOIC-16 |
| 文件頁數： | 2/8頁 |
| 文件大小： | 194K |
| 代理商： | MC74HC4020AD |
MOTOROLA
High–Speed CMOS Logic Data
DL129 — Rev 6
3–2
TSSOP Package
Tstg
TL
Storage Temperature Range
450
– 65 to + 150
C
Lead Temperature, 1 mm from Case for 10 Seconds
C
Functional operation should be restricted to the Recommended Operating Conditions.
Derating — Plastic DIP: – 10 mW/ C from 65 to 125 C
SOIC Package: – 7 mW/ C from 65 to 125 C
TSSOP Package: – 6.1 mW/ C from 65 to 125 C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
0
500
DC CHARACTERISTICS
(Voltages Referenced to GND)
VCC = 4.5 V
Symbol
Parameter
Condition
V
Guaranteed Limit
Unit
VCC
–55 to 25
°
C
≤
85
°
C
≤
125
°
C
VIH
Minimum High–Level Input Voltage
Vout = 0.1V or VCC –0.1V
|Iout|
≤
20
μ
A
2.0
3.0
4.5
6.0
1.50
2.10
3.15
4.20
1.50
2.10
3.15
4.20
1.50
2.10
3.15
4.20
V
VIL
Maximum Low–Level Input Voltage
Vout = 0.1V or VCC – 0.1V
|Iout|
≤
20
μ
A
2.0
3.0
4.5
6.0
0.50
0.90
1.35
1.80
0.50
0.90
1.35
1.80
0.50
0.90
1.35
1.80
V
VOH
Minimum High–Level Output
Voltage
Vin = VIH or VIL
|Iout|
≤
20
μ
A
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
Vin =VIH or VIL
|Iout|
≤
2.4mA
|Iout|
≤
4.0mA
|Iout|
≤
5.2mA
3.0
4.5
6.0
2.48
3.98
5.48
2.34
3.84
5.34
2.20
3.70
5.20
VOL
Maximum Low–Level Output
Voltage
Vin = VIH or VIL
|Iout|
≤
20
μ
A
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
Vin = VIH or VIL
|Iout|
≤
2.4mA
|Iout|
≤
4.0mA
|Iout|
≤
5.2mA
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.40
0.40
0.40
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance cir-
cuit. For proper operation, Vin and
Vout should be constrained to the
range GND (Vin or Vout)
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
VCC.
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