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參數(shù)資料
| 型號： | MC74HC4024N |
| 廠商： | MOTOROLA INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | 7-Stage Binary Ripple Counter |
| 中文描述： | HC/UH SERIES, ASYN NEGATIVE EDGE TRIGGERED 7-BIT UP BINARY COUNTER, PDIP14 |
| 封裝： | PLASTIC, DIP-14 |
| 文件頁數(shù)： | 3/6頁 |
| 文件大小： | 173K |
| 代理商： | MC74HC4024N |
MC74HC4024
High–Speed CMOS Logic Data
DL129 — Rev 6
3
MOTOROLA
(Figures 1 and 4)
4.5
27
18
6.0
36
22
54
tPHL
Maximum Propagation Delay, Reset to Any Q
2.0
210
265
45
315
ns
tPHL
(Figures 3 and 4)
4.5
25
38
6.0
13
31
19
Cin
NOTES:
1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
2. Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
* For TA = 25 C and CL = 50 pF, typical propagation delay from Clock to other Q outputs may be calculated with the following equations:
VCC = 2.0 V: tP = [205 + 100(N – 1)] ns
VCC = 4.5 V: tP = [41 + 20(N – 1)] ns
VCC = 6.0 V: tP = [35 + 17(N – 1)] ns
Maximum Input Capacitance
—
10
16
10
pF
10
CPD
Power Dissipation Capacitance (Per Package)*
* Used to determine the no–load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the
Motorola High–Speed CMOS Data Book (DL129/D).
Typical @ 25
°
C, VCC = 5.0 V
30
pF
Symbol
Parameter
V
Guaranteed Limit
VCC
– 55 to
25 C
125 C
trec
Minimum Recovery Time, Reset Inactive to Clock
2.0
6.0
100
17
85 C
125
150
26
Unit
ns
Minimum Pulse Width, Clock
(Figure 1)
2.0
4.5
80
16
100
21
120
24
ns
(Figure 2)
4.5
16
20
24
6.0
400
400
20
400
NOTE:Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
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