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參數(shù)資料
| 型號： | MC74HC4040ADT |
| 廠商： | MOTOROLA INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | Dual Operational Amplifier |
| 中文描述： | HC/UH SERIES, ASYN NEGATIVE EDGE TRIGGERED 12-BIT UP BINARY COUNTER, PDSO16 |
| 封裝： | PLASTIC, TSSOP-16 |
| 文件頁數(shù)： | 4/8頁 |
| 文件大小： | 215K |
| 代理商： | MC74HC4040ADT |
MC54/74HC4040A
MOTOROLA
High–Speed CMOS Logic Data
DL129 — Rev 6
4
TIMING REQUIREMENTS
(Input tr = tf = 6 ns)
Symbol
Parameter
V
Guaranteed Limit
Unit
VCC
–55 to 25
°
C
≤
85
°
C
≤
125
°
C
trec
Minimum Recovery Time, Reset Inactive to Clock
(Figure 2)
2.0
3.0
4.5
6.0
30
20
5
4
40
25
8
6
50
30
12
9
ns
tw
Minimum Pulse Width, Clock
(Figure 1)
2.0
3.0
4.5
6.0
70
40
15
13
80
45
19
16
90
50
24
20
ns
tw
Minimum Pulse Width, Reset
(Figure 2)
2.0
3.0
4.5
6.0
70
40
15
13
80
45
19
16
90
50
24
20
ns
tr, tf
Maximum Input Rise and Fall Times
(Figure 1)
2.0
3.0
4.5
6.0
1000
800
500
400
1000
800
500
400
1000
800
500
400
ns
NOTE:Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
PIN DESCRIPTIONS
INPUTS
Clock (Pin 10)
Negative–edge triggering clock input. A high–to–low tran-
sition on this input advances the state of the counter.
Reset (Pin 11)
Active–high reset. A high level applied to this input asynch-
ronously resets the counter to its zero state, thus forcing all Q
outputs low.
OUTPUTS
Q1 thru Q12 (Pins 9, 7, 6, 5, 3, 2, 4, 13, 12, 14, 15, 1)
Active–high outputs. Each Qn output divides the Clock
input frequency by 2N.
SWITCHING WAVEFORMS
tf
Clock
Q1
VCC
GND
90%
50%
10%
tr
tw
90%
50%
10%
tPHL
1/fMAX
tPLH
tTLH
tTHL
Clock
VCC
GND
tw
trec
50%
Figure 1.
Figure 2.
Reset
VCC
GND
50%
Any Q
50%
tPHL
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