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參數資料
| 型號： | MC74HC4046AD |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | XO, clock |
| 英文描述： | sensors RoHS Compliant: NA |
| 中文描述： | PHASE LOCKED LOOP, PDSO16 |
| 封裝： | SOIC-16 |
| 文件頁數： | 7/16頁 |
| 文件大小： | 290K |
| 代理商： | MC74HC4046AD |
MC74HC4046A
http://onsemi.com
7
DETAILED CIRCUIT DESCRIPTION
Voltage Controlled Oscillator/Demodulator Output
The VCO requires two or three external components to
operate. These are R1, R2, C1. Resistor R1 and Capacitor C1
are selected to determine the center frequency of the VCO
(see typical performance curves Figure 14). R2 can be used
to set the offset frequency with 0 volts at VCO input. For
example, if R2 is decreased, the offset frequency is
increased. If R2 is omitted the VCO range is from 0 Hz. The
effect of R2 is shown in Figure 24, typical performance
curves. By increasing the value of R2 the lock range of the
PLL is increased and the gain (volts/Hz) is decreased. Thus,
for a narrow lock range, large swings on the VCO input will
cause less frequency variation.
Internally, the resistors set a current in a current mirror, as
shown in Figure 5. The mirrored current drives one side of
the capacitor. Once the voltage across the capacitor charges
up to Vref of the comparators, the oscillator logic flips the
capacitor which causes the mirror to charge the opposite side
of the capacitor. The output from the internal logic is then
taken to VCO output (Pin 4).
The input to the VCO is a very high impedance CMOS
input and thus will not load down the loop filter, easing the
filters design. In order to make signals at the VCO input
accessible without degrading the loop performance, the
VCO input voltage is buffered through a unity gain Op–amp
to Demod Output. This Op–amp can drive loads of 50K
ohms or more and provides no loading effects to the VCO
input voltage (see Figure 12).
An inhibit input is provided to allow disabling of the VCO
and all Op–amps (see Figure 5). This is useful if the internal
VCO is not being used. A logic high on inhibit disables the
VCO and all Op–amps, minimizing standby power
consumption.
Figure 5. Logic Diagram for VCO
_
+
_
+
_
I1
I2
R2
12
VREF
VCOIN
R1
9
11
10
5
6
7
4
+
+
Vref
C1
(EXTERNAL)
DEMODOUT
CURRENT
MIRROR
I1 + I2 = I3
VCOOUT
INH
I3
–
–
The output of the VCO is a standard high speed CMOS
output with an equivalent LS–TTL fan out of 10. The VCO
output is approximately a square wave. This output can
either directly feed the COMPIN of the phase comparators or
feed external prescalers (counters) to enable frequency
synthesis.
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相關代理商/技術參數 |
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| MC74HC4046ADG | 功能描述:鎖相環 - PLL 3-6V 10 LSTTL Loads RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| MC74HC4046ADR2 | 功能描述:鎖相環 - PLL LOG CMOS PLL RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| MC74HC4046ADR2G | 功能描述:鎖相環 - PLL LOG CMOS PLL RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| MC74HC4046ADT | 功能描述:鎖相環 - PLL LOG CMOS PHASE RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| MC74HC4046ADTG | 功能描述:鎖相環 - PLL LOG CMOS PLL RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
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