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參數資料
| 型號： | MC74HC4046AF |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | XO, clock |
| 英文描述： | Phase-Locked Loop |
| 中文描述： | PHASE LOCKED LOOP, PDSO16 |
| 封裝： | SOEIAJ-16 |
| 文件頁數： | 8/16頁 |
| 文件大?。?/td> | 290K |
| 代理商： | MC74HC4046AF |
MC74HC4046A
http://onsemi.com
8
Phase Comparators
All three phase comparators have two inputs, SIGIN and
COMPIN. The SIGIN and COMPIN have a special DC bias
network that enables AC coupling of input signals. If the
signals are not AC coupled, standard 74HC input levels are
required. Both input structures are shown in Figure 6. The
outputs of these comparators are essentially standard 74HC
outputs (comparator 2 is TRI–STATEABLE). In normal
operation VCC and ground voltage levels are fed to the loop
filter. This differs from some phase detectors which supply
a current to the loop filter and should be considered in the
design. (The MC14046 also provides a voltage).
Figure 6. Logic Diagram for Phase Comparators
SIGIN
14
COMPIN
3
VCC
VCC
VCC
13
1
15
2
PC2OUT
PCPOUT
PC3OUT
PC1OUT
Phase Comparator 1
This comparator is a simple XOR gate similar to the
74HC86. Its operation is similar to an overdriven balanced
modulator. To maximize lock range the input frequencies
must have a 50% duty cycle. Typical input and output
waveforms are shown in Figure 7. The output of the phase
detector feeds the loop filter which averages the output
voltage. The frequency range upon which the PLL will lock
onto if initially out of lock is defined as the capture range.
The capture range for phase detector 1 is dependent on the
loop filter design. The capture range can be as large as the
lock range, which is equal to the VCO frequency range.
To see how the detector operates, refer to Figure 7. When
two square wave signals are applied to this comparator, an
output waveform (whose duty cycle is dependent on the
phase difference between the two signals) results. As the
phase difference increases, the output duty cycle increases
and the voltage after the loop filter increases. In order to
achieve lock when the PLL input frequency increases, the
VCO input voltage must increase and the phase difference
between COMPIN and SIGIN will increase. At an input
frequency equal to fmin, the VCO input is at 0 V. This
requires the phase detector output to be grounded; hence, the
two input signals must be in phase. When the input
frequency is fmax, the VCO input must be VCC and the phase
detector inputs must be 180 degrees out of phase.
Figure 7. Typical Waveforms for PLL Using
Phase Comparator 1
The XOR is more susceptible to locking onto harmonics
of the SIGIN than the digital phase detector 2. For instance,
a signal 2 times the VCO frequency results in the same
output duty cycle as a signal equal to the VCO frequency.
The difference is that the output frequency of the 2f example
is twice that of the other example. The loop filter and VCO
range should be designed to prevent locking on to
harmonics.
VCC
GND
SIGIN
COMPIN
PC1OUT
VCOIN
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相關代理商/技術參數 |
參數描述 |
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| MC74HC4046AFEL | 功能描述:鎖相環 - PLL LOG CMOS PHASE RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| MC74HC4046AFELG | 功能描述:鎖相環 - PLL LOG CMOS PLL RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| MC74HC4046AFG | 功能描述:鎖相環 - PLL LOG CMOS PLL RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| MC74HC4046AN | 功能描述:鎖相環 - PLL LOG CMOS PLL RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| MC74HC4046AND | 制造商:Motorola Inc 功能描述: |
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