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參數資料
| 型號： | MC74HC640AN |
| 廠商： | MOTOROLA INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | Octal 3-State Inverting Bus Transeceiver |
| 中文描述： | HC/UH SERIES, 8-BIT TRANSCEIVER, INVERTED OUTPUT, PDIP20 |
| 封裝： | PLASTIC, DIP-20 |
| 文件頁數： | 1/7頁 |
| 文件大小： | 151K |
| 代理商： | MC74HC640AN |
SEMICONDUCTOR TECHNICAL DATA
1
REV 7
Motorola, Inc. 1997
2/97
High–Performance Silicon–Gate CMOS
The MC54/74HC640A is identical in pinout to the LS640. The device
inputs are compatible with standard CMOS outputs; with pullup resistors,
they are compatible with LSTTL outputs.
The HC640A is a 3–state transceiver that is used for 2–way asynchronous
communication between data buses. The device has an active–low Output
Enable pin, which is used to place the I/O ports into high–impedance states.
The Direction control determines whether data flows from A to B or from B
to A.
Output Drive Capability: 15 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2 to 6 V
Low Input Current: 1
μ
A
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
Chip Complexity: 276 FETs or 69 Equivalent Gates
LOGIC DIAGRAM
A
DATA
PORT
A8
A7
A6
A5
A3
A4
A2
A1
9
8
7
6
5
4
3
2
DIRECTION
OUTPUT ENABLE
1
19
PIN 10 = GND
PIN 20 = VCC
18
17
16
15
14
13
12
11
B1
B2
B3
B4
B5
B6
B7
B8
B
DATA
PORT
FUNCTION TABLE
Control Inputs
Operation
Output
Enable
Direction
L
L
Data Transmitted from Bus B
to Bus A (Inverted)
L
H
Data Transmitted from Bus A
to Bus B (Inverted)
H
X
Buses Isolated
(High–Impedance State)
X = don’t care
PIN ASSIGNMENT
A5
A3
A2
A1
DIRECTION
GND
A8
A7
A6
A4
5
4
3
2
1
10
9
8
7
6
14
15
16
17
18
19
20
11
12
13
B3
B2
B1
OUTPUT
ENABLE
VCC
B8
B7
B6
B5
B4
DW SUFFIX
SOIC PACKAGE
CASE 751D–04
N SUFFIX
PLASTIC PACKAGE
CASE 738–03
ORDERING INFORMATION
MC54HCXXXAJ
MC74HCXXXAN
MC74HCXXXADW
Ceramic
Plastic
SOIC
J SUFFIX
CERAMIC PACKAGE
CASE 732–03
1
20
1
20
1
20
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