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參數資料
| 型號： | MC74HC646DW |
| 廠商： | MOTOROLA INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | Octal 3-State Bus Transeceivers and D Flip-Flops |
| 中文描述： | HC/UH SERIES, 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO24 |
| 封裝： | 0.300 INCH, PLASTIC, SOIC-24 |
| 文件頁數： | 10/14頁 |
| 文件大小： | 328K |
| 代理商： | MC74HC646DW |
MC54/74HC646
MOTOROLA
High–Speed CMOS Logic Data
DL129 — Rev 6
3–10
NOTES:
1. A Data Port (output) changes from the level of the storage flip–flop, QB, to the level of B Data Port (input).
2. A Data Port (output) changes from the level of the B Data Port (input) to the level of the storage flip–flop, QB.
3. The B storage flip–flop, B–to–A Source, and B Data Port (input) have simultaneously changed states for the purpose of this
3.
example. A
Data Port (output) is now displaying the voltage level of B Data Port (input).
Figure 6. A Data Port = Output, B Data Port = Input
1
2
3
B DATA PORT
A DATA PORT
OUTPUT ENABLE
DIRECTION
INTERNAL QA
(FLIP–FLOP A)
INTERNAL QB
(FLIP–FLOP B)
B–TO–A
SOURCE
A–TO–B
SOURCE
VCC
GND
VCC
GND
VCC
GND
VCC
GND
VCC
GND
VCC
GND
VCC
GND
50%
tPLH
tPHL
tPLH
tPHL
50%
PIN DESCRIPTIONS
INPUTS/OUTPUTS
A0–A7 (Pins 4–11) and B0–B7 (Pins 20–13)
A and B data ports. These pins may function either as in-
puts to or outputs from the transceivers.
CONTROL INPUTS
Output Enable (Pin 21)
Active–low output enable. When this pin is low, the outputs
are enabled and function normally. When this pin is high, the
A and B data ports are in high–impedance states. See the
Function Table.
Direction (Pin 3)
Data direction control. When the Output Enable pin is low,
this control pin determines the direction of data flow. When
Direction is high, the A data ports are inputs and the B data
ports are outputs. When Direction is low, the A data ports are
outputs and the B data ports are inputs.
A–to–B Clock, B–to–A Clock (Pins 1, 23)
Clocks for the internal D flip–flops. With a low–to–high
transition on the appropriate Clock pin, data on the A (or B)
inputs are clocked into the internal A (or B) flip–flops. These
clocks are not internally gated with the Output Enable or the
Direction pins, therefore data at the A and B pins may be
clocked into the storage flip–flops at any time.
A–to–B Source, B–to–A Source (Pins 2, 22)
Data–source selection pins. Depending upon the states of
these pins (see the Function Table), data at the outputs may
come either from the inputs or from the D flip–flops.
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