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參數資料
| 型號： | MC74HC75D |
| 廠商： | MOTOROLA INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | Dual 2-Bit Transparent Latch |
| 中文描述： | HC/UH SERIES, DUAL HIGH LEVEL TRIGGERED D LATCH, COMPLEMENTARY OUTPUT, PDSO16 |
| 封裝： | PLASTIC, SOIC-16 |
| 文件頁數： | 2/5頁 |
| 文件大小： | 172K |
| 代理商： | MC74HC75D |
MOTOROLA
High–Speed CMOS Logic Data
DL129 — Rev 6
2
(Plastic DIP or SOIC Package)
* Maximum Ratings are those values beyond which damage to the device may occur.
Derating — Plastic DIP: – 10 mW/ C from 65 to 125 C
SOIC Package: – 7 mW/ C from 65 to 125 C
260
0
400
VCC = 6.0 V
Symbol
Parameter
Test Conditions
– 55 to
25 C
125 C
6.0
4.2
85 C
4.2
4.2
Unit
Maximum Low–Level Input
Voltage
|Iout|
20
μ
A
2.0
4.5
0.3
0.9
0.3
0.9
0.3
0.9
6.0
5.9
5.9
5.9
V
Vin = VIH or VIL
4.0 mA
4.5
3.98
3.84
3.70
|Iout|
6.0
0.1
0.1
0.1
4.0 mA
5.2 mA
0.26
0.26
0.33
0.33
0.40
0.40
Iin
Maximum Input Leakage Current
Vin = VCC or GND
|Iout|
4.5
6.0
6.0
±
0.1
±
1.0
±
1.0
μ
A
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance cir-
cuit. For proper operation, Vin and
Vout should be constrained to the
range GND (Vin or Vout)
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
VCC.
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