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參數資料
| 型號： | MC74HC948E-02ADT |
| 廠商： | Motorola, Inc. |
| 英文描述： | Octal 3-State Noninverting Transparent Latch |
| 中文描述： | 八路三態同相透明鎖存器 |
| 文件頁數： | 3/7頁 |
| 文件大小： | 246K |
| 代理商： | MC74HC948E-02ADT |
MC54/74HC573A
High–Speed CMOS Logic Data
DL129 — Rev 6
3
MOTOROLA
Symbol
b l
Parameter
Test Conditions
di i
25 C
U i
Output in High–Impedance State
Vin = VIL or VIH
Vout = VCC or GND
– 55 to
0.26
125 C
Voltage
4.5
|Iout|
20
μ
A
4.5
0.1
0.4
0.1
0.1
Vin = VIH or VIL
|Iout|
≤
2.4mA
|Iout|
6.0 mA
0.33
–
Current
Maximum Three–State Leakage
A
ICC
Maximum Quiescent Supply
Vin = VCC or GND
6.0
4.0
40
160
μ
A
(CL = 50 pF, Input tr = tf = 6.0 ns)
Speed CMOS Data Book (DL129/D).
25 C
Guaranteed Limit
– 55 to
Cout
Maximum Input Capacitance
Maximum Three–State Output Capacitance (Output in High–Impedance State)
6.0
100
26
105
27
38
pF
pF
6.0
(Figures 1 and 5)
3.0
26
41
140
33
180
tPHL
6.0
(Figures 2 and 5)
3.0
26
100
38
145
34
190
tPHZ
6.0
6.0
(Figures 3 and 6)
3.0
10
100
38
15
10
15
125
33
150
tPZH
(Figures 3 and 6)
3.0
10
15
125
33
150
ns
tTHL
Maximum Output Transition Time, Any Output
(Figures 1 and 5)
2.0
3.0
60
27
75
32
13
90
36
ns
10
15
CPD
Power Dissipation Capacitance (Per Enabled Output)*
* Used to determine the no–load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the
Motorola High–Speed CMOS Data Book (DL129/D).
bl d O
Typical @ 25
°
C, VCC = 5.0 V
23
pF
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