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參數資料
型號: MC74HCT157AN
廠商: MOTOROLA INC
元件分類: 通用總線功能
英文描述: Quad 2-Input Data Selector/Multiplexer with LSTTL-Compatible Inputs
中文描述: HCT SERIES, QUAD 2 LINE TO 1 LINE MULTIPLEXER, TRUE OUTPUT, PDIP16
封裝: 648-08
文件頁數: 3/5頁
文件大?。?/td> 127K
代理商: MC74HCT157AN
MC74HCT157A
High–Speed CMOS Logic Data
DL129 — Rev 6
3
MOTOROLA
Speed CMOS Data Book (DL129/D).
Symbol
b l
Parameter
U i
500
25 C
– 55 to
85 C
125 C
ns
(Figures 3 and 4)
tPHL
(Figures 1 and 4)
tPHL
Maximum Propagation Delay, Select to Output Y
37
46
56
ns
(Figures 1 and 4)
Maximum Input Rise and Fall Time
tTHL
Maximum Output Transition Time, Any Output
15
19
22
500
500
CPD
Power Dissipation Capacitance (Per Transceiver Channel)*
* Used to determine the no–load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the
Motorola High–Speed CMOS Data Book (DL129/D).
Typical @ 25
°
C, VCC = 5.0 V
64
pF
PIN DESCRIPTIONS
INPUTS
A0, A1, A2, A3 (Pins 2, 5, 11, 14)
Nibble A inputs. The data present on these pins is trans-
ferred to the outputs when the Select input is at a low level
and the Output Enable input is at a low level. The data is
presented to the outputs in noninverted form.
B0, B1, B2, B3 (Pins 3, 6, 10, 13)
Nibble B inputs. The data present on these pins is trans-
ferred to the outputs when the Select input is at a high level
and the Output Enable input is at a low level. The data is
presented to the outputs in noninverted form.
OUTPUTS
Y0, Y1, Y2, Y3 (Pins 4, 7, 9, 12)
Data outputs. The selected input Nibble is presented at
these outputs when the Output Enable input is at a low level.
The data is presented to the outputs in noninverted form. For
the Output Enable input at a high level, the outputs are at a
low level.
CONTROL INPUTS
Select (Pin 1)
Nibble select. This input determines the data word to be
transferred to the outputs. A low level on this input selects
the A inputs and a high level selects the B inputs.
Output Enable (Pin 15)
Output Enable input. A low level on this input allows the
selected input data to be presented at the outputs. A high
level on this input sets all outputs to a low level.
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