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參數資料
型號: MC74VHCTXXXAM
廠商: Motorola, Inc.
英文描述: Octal Bus Buffer
中文描述: 八路總線緩沖器
文件頁數: 1/6頁
文件大小: 159K
代理商: MC74VHCTXXXAM
SEMICONDUCTOR TECHNICAL DATA
1
REV 0
Motorola, Inc. 1997
6/97
The MC74VHCT541A is an advanced high speed CMOS octal bus buffer
fabricated with silicon gate CMOS technology. It achieves high speed
operation similar to equivalent Bipolar Schottky TTL while maintaining
CMOS low power dissipation.
The MC74VHCT541A is a noninverting, 3–state, buffer/line driver/line
receiver. When either OE1 or OE2 is high, the terminal outputs are in the
high impedance state.
The VHCT inputs are compatible with TTL levels. This device can be used
as a level converter for interfacing 3.3V to 5.0V, because it has full 5V CMOS
level output swings.
The VHCT541A input and output (when disabled) structures provide
protection when voltages between 0V and 5.5V are applied, regardless of
the supply voltage. These input and output structures help prevent device
destruction caused by supply voltage – input/output voltage mismatch,
battery backup, hot insertion, etc.
High Speed: tPD = 5.4ns (Typ) at VCC = 5V
Low Power Dissipation: ICC = 4
μ
A (Max) at TA = 25
°
C
TTL–Compatible Inputs: VIL = 0.8V; VIH = 2.0V
Power Down Protection Provided on Inputs and Outputs
Balanced Propagation Delays
Designed for 4.5V to 5.5V Operating Range
Low Noise: VOLP = 1.6V (Max)
Pin and Function Compatible with Other Standard Logic Families
Latchup Performance Exceeds 300mA
ESD Performance: HBM > 2000V; Machine Model > 200V
Chip Complexity: 134 FETs or 33.5 Equivalent Gates
18
Y1
2
A1
17
Y2
3
A2
16
Y3
4
A3
15
Y4
5
A4
14
Y5
6
A5
13
Y6
7
A6
12
Y7
8
A7
11
Y8
9
A8
OE1
OE2
1
19
OUTPUT
ENABLES
DATA
INPUTS
NONINVERTING
OUTPUTS
LOGIC DIAGRAM
PIN ASSIGNMENT
A5
A3
A2
A1
OE1
GND
A8
A7
A6
A4
5
4
3
2
1
10
9
8
7
6
14
15
16
17
18
19
20
11
12
13
Y3
Y2
Y1
OE2
VCC
Y8
Y7
Y6
Y5
Y4
DW SUFFIX
20–LEAD SOIC PACKAGE
CASE 751D–04
ORDERING INFORMATION
MC74VHCTXXXADW
MC74VHCTXXXADT
MC74VHCTXXXAM
SOIC
TSSOP
SOIC EIAJ
DT SUFFIX
20–LEAD TSSOP PACKAGE
CASE 948E–02
M SUFFIX
20–LEAD SOIC EIAJ PACKAGE
CASE 967–01
L
L
H
X
L
L
X
H
L
H
X
X
FUNCTION TABLE
Inputs
Output Y
OE1
OE2
A
L
H
Z
Z
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