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參數資料
| 型號： | MC88921DW |
| 廠商： | MOTOROLA INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | LOW SKEW CMOS PLL CLOCK DRIVER With Power-Down/ Power-Up Feature |
| 中文描述： | 88921 SERIES, PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20 |
| 封裝： | PLASTIC, SOIC-20 |
| 文件頁數： | 7/10頁 |
| 文件大小： | 106K |
| 代理商： | MC88921DW |
MC88921
TIMING SOLUTIONS
BR1333 — REV 5
7
MOTOROLA
Figure 3. MC68040 P–Clock Input Termination Scheme
88921
2X_Q
OUTPUT
68040
P–CLOC
K
INPUT
Rs = Zo – 7
Rs
Zo (CLOCK
TRACE)
Figure 4. Logical Representation of the MC88921 With Input/Output Frequency Relationships
2X_Q
Q0
Q1
Q2
Q3
SYNC
MR
PLL_EN
16.5MHz
CRYSTAL
OSCILLATOR
66MHz P–CLOCK OUT-
PUT
33MHz
B–CLOCK
AND SYSTEM
OUTPUTS
RP
RP = 1.5Zo
Figure 5. Output/Input Switching Waveforms and Timing Relationships
SYNC Input
Q0–Q3 Outputs
2X_Q Output
tCYCLE SYNC Input
tSKEWall
tSKEWf
tSKEWr
tSKEWf
tSKEWr
Timing Notes
1. The MC88921 aligns rising edges of the outputs and the SYNC input, therefore the SYNC input does not require a 50%
duty cycle.
2. All skew specs are measured between the VCC/2 crossing point of the appropriate output edges. All skews are specified as
‘windows’, not as a
±
deviation around a center point.
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