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參數資料
| 型號： | MC88PL117 |
| 廠商： | Motorola, Inc. |
| 英文描述： | CMOS PLL CLOCK DRIVER |
| 中文描述： | 的CMOS PLL時鐘驅動器 |
| 文件頁數： | 5/11頁 |
| 文件大小： | 139K |
| 代理商： | MC88PL117 |
MC88PL117
TIMING SOLUTIONS
BR1333 — Rev 6
5
MOTOROLA
OE/MR
PLL_EN
REF_SEL
OE/MR
PLL_EN
REF_SEL
Q In (80MHz)
2X_Q (120MHz)
2X_Q (120MHz)
Q (60MHz)
Q (60MHz)
Q (60MHz)
Q (60MHz)
Q (60MHz)
Q (60MHz)
Q (60MHz)
Q (60MHz)
Q (60MHz)
Q (60MHz)
Q (60MHz)
Q (60MHz)
0
°
Phase Shift at 60MHz
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
Q12
Q13
QFEED
LOCK
Q
MC88PL117
FIL
H
H
L
SYNC0
SYNC1
FEEDBACK
OPT2
OPT1
OPT0
H
H
H
L
H
L
MULT1
MULT0
H
H
2
1
0
Q/4 In (16.5MHz)
Q (60MHz)
Q (60MHz)
Q (60MHz)
Q (60MHz)
Q (60MHz)
Q (60MHz)
Q (60MHz)
Q/2 (30MHz)
Q/2 (30MHz)
Q/2 (30MHz)
Q/2 (30MHz)
Q/2 (30MHz)
Q/2 (30MHz)
Q/2 (30MHz)
0
°
Phase Shift at 30MHz
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
Q12
Q13
QFEED
LOCK
Q
MC88PL117
FIL
H
H
L
SYNC0
SYNC1
FEEDBACK
OPT2
OPT1
OPT0
H
L
L
H
H
H
MULT1
MULT0
L
L
2
1
0
Figure 5. Output Frequency Configuration 5
(OPT0 = L, OPT1 = L, OPT2 = H
Q/4 Input Frequency, MULT0 = L, MULT1 = L)
Figure 6. Output Frequency Configuration 6
(OPT0 = H, OPT1 = H, OPT2 = H
Q Input Frequency, MULT0 = H, MULT1 = H)
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND) TA =0
°
C to + 70
°
C, VCC = 5.0 V
±
5%
Symbol
Parameter
Test Conditions
VCC
V
Target Limit
Unit
VIH
Minimum High–Level Input
Voltage
Vout = 0.1 V or VCC – 0.1 V
4.75
5.25
2.0
2.0
V
VIL
Maximum Low–Level Input
Voltage
Vout = 0.1 V or VCC – 0.1 V
4.75
5.25
0.8
0.8
V
VOH
Minimum High–Level Output
Voltage
Vin = VIH or VIL
IOH = –36 mA
1
Vin = VIH or VIL
IOL = 36 mA
1
VI = VCC or GND
VI = VCC – 2.1 V
VOLD = 1.0V Max
VOHD = 3.85V Min
VI = VCC or GND
4.75
5.25
4.01
4.51
V
VOL
Maximum Low–Level Output
Voltage
4.75
5.25
0.44
0.44
V
Iin
Maximum Input Leakage Current
5.25
±
1.0
2.0
2
88
μ
A
ICCT
IOLD
IOHD
ICC
Maximum ICC/Input
Minimum Dynamic Output Current
3
5.25
mA
5.25
mA
5.25
–88
mA
Maximum Quiescent Supply
Current (per Package)
5.25
1.0
mA
IOZ
Maximum 3–State Leakage Current
1. IOL and IOH are 12mA and –12mA respectively for the LOCK output.
2. The PLL_EN input pin is not guaranteed to meet this specification.
3. Maximum test duration is 2.0ms, one output loaded at a time.
4. Specification value for IOZ is preliminary, will be finalized upon ‘MC’ status.
VI = VIH or VIL;VO = VCC or GND
5.25
±
50
4
μ
A
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