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參數資料
| 型號： | MC88PL117FN |
| 廠商： | MOTOROLA INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | CMOS PLL CLOCK DRIVER |
| 中文描述： | 88PL SERIES, PLL BASED CLOCK DRIVER, 15 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC52 |
| 封裝： | PLASTIC, LCC-52 |
| 文件頁數： | 8/11頁 |
| 文件大小： | 139K |
| 代理商： | MC88PL117FN |
MC88PL117
MOTOROLA
TIMING SOLUTIONS
BR1333 — Rev 6
8
2X_Q output driving the 2X_PCLK input and a Q output
driving the PCLK_EN. In this implementation the BCLK_EN
input of the MPC601 is simply tied LOW.
OE/MR
PLL_EN
REF_SEL
Figure 7. 88PL117 Output Configuration 1 for
Driving the MPC601 Microprocessor
Q/4 In (15MHz)
2X_Q (120MHz)
2X_Q (120MHz)
Q (60MHz)
Q (60MHz)
Q (60MHz)
Q (60MHz)
Q/2 (30MHz)
Q/2 (30MHz)
Q/2 (30MHz)
Q/2 (30MHz)
Q/2 (30MHz)
Q/2 (30MHz)
Q/2 (30MHz)
Q/2 (30MHz)
0
°
Phase Shift at 30MHz
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
Q12
Q13
QFEED
LOCK
Q
MC88PL117
FIL
H
H
L
SYNC0
SYNC1
FEEDBACK
OPT2
OPT1
OPT0
L
L
H
H
H
H
MULT1
MULT0
L
L
2
1
0
OE/MR
PLL_EN
REF_SEL
Figure 8. 88PL117 Output Configuration 2 for
Driving the MPC601 Microprocessor
Q/2 In (25MHz)
2X_Q (100MHz)
2X_Q (100MHz)
Q (50MHz)
Q (50MHz)
Q (50MHz)
Q (50MHz)
Q (50MHz)
Q (50MHz)
Q (50MHz)
Q (50MHz)
Q (50MHz)
Q (50MHz)
Q (50MHz)
Q (50MHz)
0
°
Phase Shift at 50MHz
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
Q12
Q13
QFEED
LOCK
Q
MC88PL117
FIL
H
H
L
SYNC0
SYNC1
FEEDBACK
OPT2
OPT1
OPT0
L
L
L
L
H
L
MULT1
MULT0
L
H
2
1
0
Driving the PowerPC 601 Microprocessor
Figures 9 and 10 illustrate the required waveforms for
driving the MPC601 processor in both bus clock frequency
modes. Figure 10 illustrates the relationship between the
2X_Q, Q and Q/2 outputs of the 88PL117. For the case of the
BCLK_EN input being held LOW, the setup and hold
specifications for PCLK_EN are automatically satisfied by the
internal design of the 88PL117. For the first case pictured in
Figure 9, there may be a potential problem: the hold time
spec for BCLK_EN rising to 2X_PCLK is 0ns. Because there
can be up to
±
250ps skew between the 2X_Q and Q/2
outputs of the 88PL117, this hold spec may be violated. This
situation can be remedied in one of two ways: first extra PCB
etch can be added to the Q/2 output to delay it relative to the
2X_Q output; or secondly, the Q
output can be used to
drive the BCLK_EN input. The Q
output can be phase
delayed relative to the 2X_Q output to ensure the hold time
requirement of the MPC601 processor will be met.
Figure 9. MPC601 Processor Clocking Waveforms
2X_PCLK
PCLK_EN
BCLK_EN
2X_PCLK
PCLK_EN
BCLK_EN
1/2 FREQUENCY BUS CLOCKING
FULL FREQUENCY BUS CLOCKING
Figure 10. 88PL117 Output Waveforms
2X_Q
Q
Q/2
Q
(45
°
)
The 88PL117 features CMOS level outputs to minimize
edge transition time and optimize transmission line driving
capability. The MPC601 processor inputs are TTL level
compatible inputs and therefore specification limits are
calculated from TTL level thresholds. The specification limits
of concern are the input duty cycle and input pulse width
requirements outlined in the MPC601 specification for the
2X_PCLK input. Figure 11 demonstrates the termination
technique required on the 2X_Q output of the 88PL117 to
ensure compatibility with the 2X_PCLK input of the MPC601
processor. At 100 or 120MHz, the 2X_Q output threshold
must be shifted down to the 1.4V threshold to meet the input
pulse width specification limits. The termination scheme in
Figure 11 creates a voltage division which essentially
translates the CMOS threshold down to a TTL threshold,
while at the same time effectively terminating the
transmission line. The 88PL117 exhibits a very tight duty
cycle specification at CMOS thresholds. Therefore, once
translated via the termination scheme of Figure 11, the
MPC601 processor input specifications are easily met.
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