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MCF5206 PRODUCT INFORMATION
MOTOROLA
Internal SRAM
The 512-byte on-chip SRAM provides one clock-cycle access for the ColdFire core. This SRAM can store
processor stack and critical code or data segments to maximize performance.
DRAM Controller
The MCF5206 DRAM controller provides a glueless interface for up to 2 banks of DRAM, each of which can
be from 128 Kbytes up to 256 Mbytes in size. The controller supports an 8-, 16-, or 32-bit data bus. A unique
addressing scheme allows for increases in system memory size without rerouting address lines and rewiring
boards. The controller operates in full-page mode, burst-page mode, or in regular mode, and supports
extended-data-out (EDO) DRAMs. At 33Mhz, the DRAM controller supports DRAMs with access times as fast
as 60ns.
DUART Module
A full duplex DUART module contains independent receivers and transmitters that can be clocked by the
DUART internal timer. This timer is clocked by the system clock or an external clock supplied by the TIN pin.
Data formats can be 5, 6, 7, or 8 bits with even, odd, or no parity, and up to 2 stop bits in 1/16 increments.
Four-byte receive buffers and two-byte transmit buffers minimize CPU service calls. The DUART module also
provides several error-detection and maskable-interrupt capabilities. Modem support includes request-to-send
(RTS) and clear-to-send (CTS) lines.
The system clock provides the clocking function via a programmable prescaler. Users can select full duplex,
autoecho loopback, local loopback, and remote loopback modes. The programmable DUART can interrupt the
CPU on various normal or error-condition events.
Timer Module
The timer module includes 2 general-purpose timers, each of which contains a free-running 16-bit timer for use
in any of 3 modes. One mode captures the timer value with an external event. Another mode triggers an
external signal or interrupts the CPU when the timer reaches a set value, while a third mode counts external
events. The timer unit has an 8-bit prescaler that allows programming of the clock input frequency, which is
derived from the system clock. The programmable timer-output pin generates either an active-low pulse or
toggles the output.
Motorola Bus (M-Bus) Module
The M-Bus interface is a two-wire, bidirectional serial bus that exchanges data between devices and is
compatible with the I
C Bus standard. The M-Bus minimizes the interconnection between devices in the end
system and is best suited for applications that need occasional bursts of rapid communication over short
distances among several devices. Bus capacitance and the number of unique addresses limit the maximum
communication length and the number of devices that can be connected.
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System Interface
The MCF5206 processor provides a glueless interface to 8-, 16-, and 32-bit port size SRAM, ROM, and
peripheral devices with independent programmable control of the assertion and negation of chip-selects and
write-enables. Programmable address and data-hold times can be extended for a compatible interface to
external devices and memory. The MCF5206 also supports bursting ROMs.
External Bus Interface.
memory, peripherals, or other masters on the external bus. The external bus interface provides up to 28 bits
of address bus space, a 32-bit data bus, and all associated control signals. This interface implements an
extended synchronous protocol that supports bursting operations. For nonsynchronous external memory and
peripherals, the MCF5206 processor provides an alternate asynchronous bus transfer acknowledgment
signal.
The bus interface controller transfers information between the ColdFire core and
Simple two-wire request/acknowledge bus arbitration between the MCF5206 processor and another bus
master, such as a DMA device, is glueless with arbitration handled internal to the MCF5206 processor.
Alternately, an external bus arbiter can control more complex three-wire (request, grant, busy) multiple-master
bus arbitration, allowing overlapped bus arbitration with one clock-bus handovers.
Chip-Selects.
Eight programmable chip-select outputs provide signals that enable external memory and