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參數資料
| 型號： | MCM44D256B |
| 廠商： | Motorola, Inc. |
| 英文描述： | 4MB R4000 Secondary Cache Fast Static RAM Module Set |
| 中文描述： | 二級緩存4MB的R4000的快速靜態存儲器模塊集 |
| 文件頁數： | 4/8頁 |
| 文件大小： | 81K |
| 代理商： | MCM44D256B |
MCM44256B SERIES
4
MOTOROLA FAST SRAM
AC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V
±
10%, TA = 0 to + 70
°
C, Unless Otherwise Noted)
Input Timing Measurement Reference Level
Input Pulse Levels
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Rise/Fall Time
. . . . . . . . . . . . . . . . . . . . . .
1.5 V
. . . . . . . . . . . . . . .
0 to 3.0 V
1 V/ns (20% to 80%)
Output Timing Measurement Reference Level
Output Load
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5 V
. . . . . . . . . . . . .
See Figure 1
READ CYCLE
(See Notes 1 and 2)
Parameter
Symbol
b l
–12
–15
–17
U i
Unit
Notes
Min
Max
Min
Max
Min
Max
Address Access Time
tAVQV
tA0AQV
tELQV
tGLQV
tAXQX
tA0XQX
tELQX
tEHQZ
tGLQX
tGHQZ
—
12
—
15
—
17
ns
A0 Access Time
—
10
—
12
—
14
ns
Data/Tag Enable Access Time
—
12
—
15
—
17
ns
Output Enable Access Time
—
9
—
10
—
11
ns
Output Hold from Address Change
4
—
4
—
4
—
ns
Output Hold from A0 Change
4
—
4
—
4
—
ns
Data/Tag Enable Low to Output Active
2
—
2
—
2
—
ns
3, 4
Data/Tag Enable High to Output High–Z
1
9
1
10
1
11
ns
3, 4
Output Enable Low to Output Active
1
—
1
—
1
—
ns
3, 4
Output Enable High to Output High–Z
1
9
1
10
1
11
ns
3, 4
NOTES:
1. WE is high for read cycle.
2. Enable timings are the same for both DCS and TCS.
3. Transition is measured 200 mV from steady–state voltage.
4. This parameter is sampled and not 100% tested.
The table of timing values shows either a minimum
or a maximum limit for each parameter. Input require-
ments are specified from the external system point of
view. Thus, address setup time is shown as a mini-
mum since the system must supply at least that much
time. On the other hand, responses from the memory
are specified from the device point of view. Thus, the
access time is shown as a maximum since the device
never provides data later than that time.
TIMING LIMITS
OUTPUT
Z0 = 50
RL = 50
VL = 1.5 V
Figure 1. AC Test Load
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