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參數資料
| 型號： | MCM6205DJ25R2 |
| 廠商： | MOTOROLA INC |
| 元件分類： | SRAM |
| 英文描述： | 32K x 9 Bit Fast Static RAM |
| 中文描述： | 32K X 9 STANDARD SRAM, 25 ns, PDSO32 |
| 封裝： | 0.300 INCH, PLASTIC, SOJ-32 |
| 文件頁數： | 1/8頁 |
| 文件大小： | 143K |
| 代理商： | MCM6205DJ25R2 |
MCM6205D
1
Motorola, Inc. 1994
32K x 9 Bit Fast Static RAM
The MCM6205D is fabricated using Motorola’s high–performance silicon–gate
CMOS technology. Static design eliminates the need for external clocks or timing
strobes, while CMOS circuitry reduces power consumption and provides for
greater reliability.
This device meets JEDEC standards for functionality and pinout, and is avail-
able in a plastic small–outline J–leaded package.
Single 5 V
±
10% Power Supply
Fully Static — No Clock or Timing Strobes Necessary
Fast Access Times: 15, 20, and 25 ns
Equal Address and Chip Enable Access Times
Output Enable (G) Feature for Increased System Flexibility and to
Eliminate Bus Contention Problems
Low Power Operation: 130 – 140 mA Maximum AC
Fully TTL Compatible — Three State Output
BLOCK DIAGRAM
A0
A2
A5
A8
A12
A13
A14
A1
A3
A4
A6
A7
A9
A10
A11
MEMORY MATRIX
256 ROWS x
128 x 9 COLUMNS
ROW
DECODER
INPUT
DATA
CONTROL
COLUMN I/O
COLUMN DECODER
DQ0
DQ8
E2
E1
W
G
VCC
VSS
Order this document
by MCM6205D/D
SEMICONDUCTOR TECHNICAL DATA
PIN ASSIGNMENT
MCM6205D
J PACKAGE
300 MIL SOJ
CASE 857–02
NC
A8
A7
A6
A5
A4
A3
A2
A1
VSS
V
A14
E2
A13
CC
A9
A10
A0
NC
A11
A12
DQ7
DQ8
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
DQ0
DQ1
DQ2
DQ3
DQ6
DQ4
DQ5
W
G
E1
PIN NAMES
A0 – A14
DQ0 – DQ8
W
. . . . . . . . . . . . . . . . . . . .
G
. . . . . . . . . . . . . . . . . . .
E1, E2
. . . . . . . . . . . . . . . . .
NC
. . . . . . . . . . . . . . . . .
VCC
. . . . . . . . . . .
VSS
. . . . . . . . . . . . . . . . . . . . . . .
Address Input
. . . . . . . . . . . . .
Data Input/Data Output
. . .
Write Enable
Output Enable
Chip Enable
No Connection
Power Supply (+ 5 V)
Ground
REV 1
5/95
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