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參數資料
| 型號： | MCM6206BBEJ25R |
| 廠商： | MOTOROLA INC |
| 元件分類： | SRAM |
| 英文描述： | 32K x 8 Bit Fast Static RAM |
| 中文描述： | 32K X 8 STANDARD SRAM, 25 ns, PDSO28 |
| 封裝： | 0.300 INCH, PLASTIC, SOJ-28 |
| 文件頁數： | 3/8頁 |
| 文件大?。?/td> | 108K |
| 代理商： | MCM6206BBEJ25R |
MCM6206BB
3
MOTOROLA FAST SRAM
AC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V
±
10%, TA = 0 to + 70
°
C, Unless Otherwise Noted)
Input Timing Measurement Reference Level
Input Pulse Levels
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Rise/Fall Time
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5 V
. . . . . . . . . . . . . . .
0 to 3.0 V
5 ns
Output Timing Measurement Reference Level
Output Load
. . . . . . . . . . . . . . . . . .
1.5 V
. . . . . . . . . . . . .
Figure 1 Unless Otherwise Noted
READ CYCLE
(See Note 1)
– 12
– 15
– 20
– 25
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Min
Max
Unit
Notes
Read Cycle Time
tAVAV
tAVQV
tELQV
tGLQV
tAXQX
tELQX
tEHQZ
tGLQX
tGHQZ
tELICCH
tEHICCL
12
—
15
—
20
—
25
—
ns
2
Address Access Time
—
12
—
15
—
20
—
25
ns
Enable Access Time
—
12
—
15
—
20
—
25
ns
3
Output Enable Access Time
—
6
—
8
—
10
—
12
ns
Output Hold from Address Change
3
—
3
—
3
—
3
—
ns
4,5,6
Enable Low to Output Active
4
—
4
—
4
—
4
—
ns
4,5,6
Enable High to Output High–Z
—
7
—
8
—
9
—
10
ns
4,5,6
Output Enable Low to Output Active
0
—
0
—
0
—
0
—
ns
4,5,6
Output Enable High to Output High–Z
—
6
—
7
—
8
—
10
ns
4,5,6
Power Up Time
0
—
0
—
0
—
0
—
ns
Power Down Time
—
12
—
15
—
20
—
25
ns
NOTES:
1. W is high for read cycle.
2. All timings are referenced from the last valid address to the first transitioning address.
3. Addresses valid prior to or coincident with E going low.
4. At any given voltage and temperature, tEHQZ (max) is less than tELQX (min), and tGHQZ (max) is less than tGLQX (min), both for a given
device and from device to device.
5. Transition is measured
±
500 mV from steady–state voltage.
6. This parameter is sampled and not 100% tested.
7. Device is continuously selected (E = VIL, G = VIL).
OUTPUT
Z0 = 50
50
VL = 1.5 V
TIMING LIMITS
The table of timing values shows either a
minimum or a maximum limit for each param-
eter. Input requirements are specified from
the external system point of view. Thus, ad-
dress setup time is shown as a minimum
since the system must supply at least that
much time. On the other hand, responses
from the memory are specified from the de-
vice point of view. Thus, the access time is
shown as a maximum since the device never
provides data later than that time.
Figure 1. AC Test Loads
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