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參數資料
| 型號： | MCM6206DP20 |
| 廠商： | MOTOROLA INC |
| 元件分類： | SRAM |
| 英文描述： | 32K x 8 Bit Fast Static RAM |
| 中文描述： | 32K X 8 STANDARD SRAM, 20 ns, PDIP28 |
| 封裝： | 0.300 INCH, PLASTIC, DIP-28 |
| 文件頁數： | 3/8頁 |
| 文件大小： | 162K |
| 代理商： | MCM6206DP20 |
MCM6206D
3
MOTOROLA FAST SRAM
AC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V
±
10%, TA = 0 to + 70
°
C, Unless Otherwise Noted)
Input Timing Measurement Reference Level
Input Pulse Levels
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Rise/Fall Time
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5 V
. . . . . . . . . . . . . . .
0 to 3.0 V
5 ns
Output Timing Measurement Reference Level
Output Load
. . . . . . . . . . . . . . . .
1.5 V
. . . . . . . . . . . . .
Figure 1A Unless Otherwise Noted
READ CYCLE
(See Note 1)
– 12
– 15
– 20
– 25
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Min
Max
Unit
Notes
Read Cycle Time
tAVAV
tAVQV
tELQV
tGLQV
tAXQX
tELQX
tEHQZ
tGLQX
tGHQZ
tELICCH
tEHICCL
12
—
15
—
20
—
25
—
ns
2
Address Access Time
—
12
—
15
—
20
—
25
ns
Enable Access Time
—
12
—
15
—
20
—
25
ns
3
Output Enable Access Time
—
6
—
8
—
10
—
12
ns
Output Hold from Address Change
4
—
4
—
4
—
4
—
ns
4,5,6
Enable Low to Output Active
4
—
4
—
4
—
4
—
ns
4,5,6
Enable High to Output High–Z
0
7
0
8
0
9
0
10
ns
4,5,6
Output Enable Low to Output Active
0
—
0
—
0
—
0
—
ns
4,5,6
Output Enable High to Output High–Z
0
6
0
7
0
8
0
10
ns
4,5,6
Power Up Time
0
—
0
—
0
—
0
—
ns
Power Down Time
—
12
—
15
—
20
—
25
ns
NOTES:
1. W is high for read cycle.
2. All timings are referenced from the last valid address to the first transitioning address.
3. Addresses valid prior to or coincident with E going low.
4. At any given voltage and temperature, tEHQZ (max) is less than tELQX (min), and tGHQZ (max) is less than tGLQX (min), both for a
given device and from device to device.
5. Transition is measured
±
500 mV from steady–state voltage with load of Figure 1B.
6. This parameter is sampled and not 100% tested.
7. Device is continuously selected (E = VIL, G = VIL).
AC TEST LOADS
OUTPUT
Z0 = 50
50
VL = 1.5 V
Figure 1A
Figure 1B
5 pF
+5 V
OUTPUT
255
480
TIMING LIMITS
The table of timing values shows either a
minimum or a maximum limit for each param-
eter. Input requirements are specified from
the external system point of view. Thus, ad-
dress setup time is shown as a minimum
since the system must supply at least that
much time (even though most devices do not
require it). On the other hand, responses from
the memory are specified from the device
point of view. Thus, the access time is shown
as a maximum since the device never pro-
vides data later than that time.
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