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參數資料
| 型號： | MCM6206DP25 |
| 廠商： | MOTOROLA INC |
| 元件分類： | SRAM |
| 英文描述： | 32K x 8 Bit Fast Static RAM |
| 中文描述： | 32K X 8 STANDARD SRAM, 25 ns, PDIP28 |
| 封裝： | 0.300 INCH, PLASTIC, DIP-28 |
| 文件頁數： | 5/8頁 |
| 文件大小： | 162K |
| 代理商： | MCM6206DP25 |
MCM6206D
5
MOTOROLA FAST SRAM
WRITE CYCLE 1
(W Controlled, See Notes 1 and 2)
– 12
– 15
– 20
– 25
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Min
Max
Unit
Notes
Write Cycle Time
tAVAV
tAVWL
tAVWH
tWLWH,
tWLEH
12
—
15
—
20
—
25
—
ns
3
Address Setup Time
0
—
0
—
0
—
0
—
ns
Address Valid to End of Write
10
—
12
—
15
—
20
—
ns
Write Pulse Width
10
—
12
—
15
—
20
—
ns
Write Pulse Width,
G High
tWLWH,
tWLEH
10
—
10
—
12
—
15
—
ns
4
Data Valid to End of Write
tDVWH
tWHDX
tWLQZ
tWHQX
tWHAX
6
—
7
—
8
—
10
—
ns
Data Hold Time
0
—
0
—
0
—
0
—
ns
Write Low to Output High–Z
0
6
0
7
0
8
0
10
ns
5,6,7
Write High to Output Active
4
—
4
—
4
—
4
—
ns
5,6,7
Write Recovery Time
0
—
0
—
0
—
0
—
ns
NOTES:
1. A write occurs during the overlap of E low and W low.
2. If G goes low coincident with or after W goes low, the output will remain in a high impedance state.
3. All timings are referenced from the last valid address to the first transitioning address.
4. If G
≥
VIH, the output will remain in a high impedance state.
5. At any given voltage and temperature, tWLQZ (max) is less than tWHQX (min), both for a given device and from device to device.
6. Transition is measured
±
500 mV from steady–state voltage with load of Figure 1B.
7. This parameter is sampled and not 100% tested.
WRITE CYCLE 1
(W Controlled, See Notes 1 and 2)
DATA VALID
tDVWH
tAVWL
tAVWH
tAVAV
tWHAX
tWLWH
tWLEH
tWHDX
tWLQZ
tWHQX
HIGH–Z
HIGH–Z
A (ADDRESS)
W (WRITE ENABLE)
E (CHIP ENABLE)
Q (DATA OUT)
D (DATA IN)
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