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參數資料
| 型號： | MCM6246WJ25 |
| 廠商： | MOTOROLA INC |
| 元件分類： | DRAM |
| 英文描述： | 512K x 8 Bit Static Random Access Memory |
| 中文描述： | 512K X 8 STANDARD SRAM, 25 ns, PDSO36 |
| 封裝： | 0.400 INCH, SOJ-36 |
| 文件頁數： | 6/8頁 |
| 文件大小： | 126K |
| 代理商： | MCM6246WJ25 |
MCM6246
6
MOTOROLA FAST SRAM
WRITE CYCLE 2
(E Controlled, See Notes 1, 2, and 3)
MCM6246–17
MCM6246–20
MCM6246–25
MCM6246–35
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Min
Max
Unit
Notes
Write Cycle Time
tAVAV
tAVEL
tAVEH
tELEH,
tELWH
17
—
20
—
25
—
35
—
ns
4
Address Setup Time
0
—
0
—
0
—
0
—
ns
Address Valid to End of Write
14
—
14
—
17
—
20
—
ns
Enable Pulse Width
14
—
14
—
17
—
20
—
ns
5,6
Write Pulse Width
tWLEH
tDVEH
tEHDX
tEHAX
14
—
14
—
17
—
20
—
ns
Data Valid to End of Write
9
—
10
—
10
—
15
—
ns
Data Hold Time
0
—
0
—
0
—
0
—
ns
Write Recovery Time
0
—
0
—
0
—
0
—
ns
NOTES:
1. A write occurs during the overlap of E low and W low.
2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus conten-
tion conditions during read and write cycles.
3. If G goes low coincident with or after W goes low, the output will remain in a high–impedance state.
4. All write cycle timing is referenced from the last valid address to the first transitioning address.
5. If E goes low coincident with or after W goes low, the output will remain in a high impedance condition.
6. If E goes high coincident with or before W goes high, the output will remain in a high impedance condition.
WRITE CYCLE 2
(E Controlled, See Notes 1, 2, and 3)
DATA VALID
HIGH–Z
tAVAV
tAVEH
tAVEL
tELWH
tEHAX
tDVEH
tEHDX
A (ADDRESS)
E (CHIP ENABLE)
W (WRITE ENABLE)
D (DATA IN)
Q (DATA OUT)
tELEH
tWLEH
ORDERING INFORMATION
(Order by Full Part Number)
Motorola Memory Prefix
Part Number
Package (WJ = 400 mil SOJ)
Full Part Numbers — MCM6246WJ17
MCM6246WJ17R2
MCM6246WJ20R2
MCM6246WJ25R2
MCM6246WJ35R2
MCM6246WJ20
MCM6246WJ25
MCM6246WJ35
Shipping Method (R2 = Tape and Reel, Blank = Rails)
Speed (17 = 17 ns, 20 = 20 ns, 25 = 25 ns,
35 = 35 ns)
MCM
6246
XX
XX
XX
相關PDF資料 |
PDF描述 |
|---|---|
| MCM6246WJ35R2 | 512K x 8 Bit Static Random Access Memory |
| MCM6246WJ35 | 512K x 8 Bit Static Random Access Memory |
| MCM6246WJ25R2 | 512K x 8 Bit Static Random Access Memory |
| MCM6246WJ17 | DC-DC Converter; Supply Voltage:75V; Output Voltage:1.2V; Number of Outputs:1; Power Rating:100W; Mounting Type:PC Board; Series:Eighth-Brick; Efficiency:86%; Output Current:50A; Peak Reflow Compatible (260 C):Yes RoHS Compliant: Yes |
| MCM6246WJ17R2 | PSU, 110W, 4 OUTPUT; Voltage, output:5V; Current, output:11A; Power rating:110W; Voltage, supply min:85V; Voltage, supply max:264V; Length / Height, external:56mm; Width, external:108mm; Depth, external:185mm; Approval Bodies:VDE, RoHS Compliant: Yes |
相關代理商/技術參數 |
參數描述 |
|---|---|
| MCM6246WJ25R2 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:512K x 8 Bit Static Random Access Memory |
| MCM6246WJ35 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:512K x 8 Bit Static Random Access Memory |
| MCM6246WJ35R2 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:512K x 8 Bit Static Random Access Memory |
| MCM62486AFN24 | 制造商:Motorola Inc 功能描述: |
| MCM62486B | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:32K x 9 Bit BurstRAM Synchronous Static RAM |
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