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參數資料
| 型號： | MCM62Y308 |
| 廠商： | Motorola, Inc. |
| 英文描述： | Synchronous Line Buffer:8K x 8 Bit Fast Static Dual Ported Memory |
| 中文描述： | 同步線緩沖區器：8K × 8位快速靜態雙端口存儲器 |
| 文件頁數： | 11/16頁 |
| 文件大小： | 257K |
| 代理商： | MCM62Y308 |
MCM62Y308
11
MOTOROLA FAST SRAM
DEVICE SPECIFIC (PUBLIC) INSTRUCTIONS
LDCONT TAP INSTRUCTION
The Control Register is an eight bit register that contains the
control bits for the Address Registers and Counters and the
Output Enable pin. When the LDCONT TAP instruction is
loaded into the Instruction Register, the Control Register is
placed between TDI and TDO when the TAP controller is in the
Shift–DR state (see Figure 2 and Table 10). The power–up/
preload state and function of the Control bits are found in
Table 3.
The Expand ID bits provide system depth expansion. These
three bits are compared to the upper three bits in the address
counters. As long as the three Expand–ID bits match the three
upper bits in the address counters the port will stay active. If
they do not match, the port will deactivate (i.e., outputs will
High–Z or write will be disabled); however, the counters will
continue counting as long as RE and WE remain asserted
(i.e., high) at the rising edge of Clock.
The Reload Control bits (3 and 5) are used to control either
reloading the Read and Write Address Counters from the
Reload Registers or clearing the counter when RR or WR is
asserted. If these bits are set low the counters they control will
be cleared to all zeroes if the appropriate reload signal (RR or
WR) is asserted and any value in the Reload Register is ig-
nored. This means that if the initial address value desired is
address 0000 (or FFFF when counting down) then there is no
need to load the Address Reload Registers using the
LDRREG, LDWREG, or the LDBREG instructions in the fol-
lowing description. If these bits are set high the counters are
loaded up with the values in the Reload Registers when the
appropriate reload signal (RR or WR) is asserted.
The Up/Down count bits (4 and 6) determine the direction
in which the respective Address Counter will count; if the bit
is set low the counter will count up and if set high the counter
will count down. If the counters are set to count down and the
Reload control is set to the clear counter mode, then the initial
value in the counters will be FFFF. To ensure that the counter
will function properly, a reload (using RR or WR) is required
after the count direction is switched.
The Output Enable control bit (7) determines the function-
ality of the Output Enable pin, G. When the bit is low, G func-
tions asynchronously. When set high, G functions
synchronously and must meet the specified setup and hold ti-
mes to the Clock K.
The Control Register will also be preloaded. When the
instruction 0010 (LDCONT) is in the Instruction Register and
the controller is in the Capture–DR state the above preload
values (all zeroes) will be loaded into the Control Register. All
zeroes will also be loaded in the Control Register at power–up.
While new values are shifted in from TDI in the Shift–DR
state, all zeroes will be output on TDO for the first eight bits.
LDRREG, LDWREG, AND LDBREG TAP INSTRUCTIONS
There are three instructions that may be used to load the 16
bit address reload registers: LDRREG (Load Read Address
Reload Register), LDWREG (Load Write Address Reload
Register), and LDBREG (Load both Address Reload Regis-
ters, Write followed by Read). Figure 2 illustrates how the Re-
load registers are placed between TDI and TDO. Tables 7, 8,
and 9 describe each register. These instructions would be
used only if the user needed to load the Reload Registers with
a non–zero value. If the Address Counters are to always be
reset to zeroes (or all 1s if counting down) then only the Con-
trol Register need be loaded to affect a reset of the counters.
The TAP controller has been set up to make it easier for the
user to serially load the Reload Registers. When the TAP con-
troller is clocked into the Capture–IR state (see state diagram)
the instruction for loading both registers (0101) will be pre-
loaded into the shift register. This allows the user to go directly
to the Update–IR instead of having to serially shift this instruc-
tion in through the TDI port. Once the load instruction has been
entered the user can then clock over to the Capture–DR state
where the value for the reload register(s) is serially loaded
(see Figure 2).
RDCOUNT TAP INSTRUCTION
The RDCOUNT scan register is accessible after the
RDCOUNT instruction is loaded into the TAP instruction regis-
ter in the Shift–IR state and the TAP controller is then moved
to the Shift–DR state. This scan register can then be used to
shift out the values of the Read and Write Address Counters
The RDCOUNT scan–register is a sample only register and
can not be used to load values into the counters. See Table 4.
EZWRITE TAP INSTRUCTION AND SCAN PATH
The EZWRITE TAP instruction is provided to allow the user
to more easily and quickly write a large number of bytes to the
device serially through the TDI port. EZWRITE shortens the
scan path for a serial write to just the 8 bit Data in register (see
Table 5).
The most likely use of this instruction is as follows: the user
would first load the Control Register using the LDCONT
instruction. This would initialize the Expand ID bits and the
Write Counter. The Write Reload Register will need to be
Table 3. Control Register Bit Description
Bit
No.
Power Up and
Preload State
Function
0 – 2
000
Expand ID bits for comparison with the upper 3 bits of the Read and Write Address counters
3
0
Reload Control of Write Address Counter (0 = clear counter, 1 = reload)
4
0
Up/Down count bit for Write Address Counter (0 = count up, 1 = count down)
5
0
Reload Control of Read Address Counter (0 = clear counter, 1 = reload)
6
0
Up/Down count bit for Read Address Counter (0 = count up, 1 = count down)
7
0
G Control (0 = asynchronous, 1 = synchronous)
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