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參數(shù)資料
型號: MCM6323ATS12R
廠商: MOTOROLA INC
元件分類: SRAM
英文描述: 64K x 16 Bit 3.3 V Asynchronous Fast Static RAM
中文描述: 64K X 16 STANDARD SRAM, 12 ns, PDSO44
封裝: TSOP2-44
文件頁數(shù): 9/12頁
文件大小: 181K
代理商: MCM6323ATS12R
MCM6323A
9
MOTOROLA FAST SRAM
WRITE CYCLE 3
(B Controlled, See Notes 1 and 2)
Parameter
Symbol
b l
MCM6323A–10
MCM6323A–12
MCM6323A–15
U i
Unit
Notes
Min
Max
Min
Max
Min
Max
Write Cycle Time
tAVAV
tAVBL
tAVBH
tWLWH,
tWLEH
10
12
15
ns
3
Address Setup Time
0
0
0
ns
Address Valid to End of Write
8
9
10
ns
Write Pulse Width
8
9
10
ns
Byte Pulse Width
tBLWH,
tBLEH,
tBLBH
tDVBH
tBHDX
tWLQZ
tWHQX
tBHAX
8
9
10
ns
Data Valid to End of Write
5
6
7
ns
Data Hold Time
0
0
0
ns
Write Low to Data High–Z
0
4
0
5
0
6
ns
4, 5, 6
Write High to Output Active
3
3
3
ns
4, 5, 6
Write Recovery Time
0
0
0
ns
NOTES:
1. A write occurs during the overlap of E low, W low, and LB and/or UB low.
2. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycles.
3. All write cycle timings are referenced from the last valid address to the first transitioning address.
4. Transition is measured 200 mV from steady–state voltage.
5. At any given voltage and temperature, tWLQZ max < tWHQX min both for a given device and from device to device.
6. This parameter is sampled and not 100% tested.
WRITE CYCLE 3
(B Controlled)
DATA VALID
tDVBH
tAVBL
tAVBH
tAVAV
tBHAX
tBLWH
tBLBH
tBHDX
tWLQZ
tWHQX
HIGH–Z
HIGH–Z
A (ADDRESS)
W (WRITE ENABLE)
E (CHIP ENABLE)
Q (DATA OUT)
D (DATA IN)
tBLEH
tWLWH
LB, UB (BYTE ENABLE)
tWLEH
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