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參數資料
| 型號： | MCM63P531TQ8R |
| 廠商： | MOTOROLA INC |
| 元件分類： | SRAM |
| 英文描述： | 32K x 32 Bit Pipelined BurstRAM Synchronous Fast Static RAM |
| 中文描述： | 32K X 32 CACHE SRAM, 8 ns, PQFP100 |
| 封裝： | TQFP-100 |
| 文件頁數： | 7/27頁 |
| 文件大小： | 328K |
| 代理商： | MCM63P531TQ8R |
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MCM63P636
7
MOTOROLA FAST SRAM
HIGH–Z4
INTERMEDIATE
HIGH–Z1, 4
Figure 2. Data I/O State Diagram
D, CW, CR – MW
BR
CR
CR
CR
D, CW, CR
CW, MW
MW
CW, MW
NOTES:
1. Command code inputs not shown from this state are not valid.
2. STRBA and STRBB transition from logic 1 to 0. STRBA and STRBB transition from logic 0 to 1.
3. STRBA and STRBB transition from logic 0 to 1. STRBA and STRBB transition from logic 1 to 0.
4. Data strobes are driven to High–Z.
INTERMEDIATE
HIGH–Z1, 4
DATA–OUT/
Q(1)VALID1, 2
DATA–OUT/
Q(2)VALID1, 3
DATA–OUT/
Q(3)VALID1, 2
DATA–OUT/
Q(4)VALID1, 3
DATA–OUT/
Q(4)VALID1, 3
DATA–IN (1)/
HIGH–Z1, 4
CW
CW
CW
DATA–IN (2)/
HIGH–Z1, 4
DATA–IN (3)/
HIGH–Z1, 4
DATA–IN (4)/
HIGH–Z1, 4
MASK (2)/
HIGH–Z1, 4
MW
MW
MW
MASK (3)/
HIGH–Z1, 4
MASK (4)/
HIGH–Z1, 4
HIGH–Z1, 4
MW
MW
MW
HIGH–Z1, 4
BR
CR
BR
CR
BW
CR
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