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參數資料
| 型號： | MCM63P631A |
| 廠商： | Motorola, Inc. |
| 英文描述： | 64K x 32 Bit Pipelined BurstRAM Synchronous Fast Static RAM |
| 中文描述： | 64K的× 32位流水線BurstRAM同步快速靜態存儲器 |
| 文件頁數： | 9/16頁 |
| 文件大小： | 228K |
| 代理商： | MCM63P631A |
MCM63P631A
9
MOTOROLA FAST SRAM
AC OPERATING CONDITIONS AND CHARACTERISTICS
(VDD = 3.3 V + 10%, – 5%, TA = 0 to 70
°
C, Unless Otherwise Noted)
Input Timing Measurement Reference Level
Input Pulse Levels
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Rise/Fall Time
. . . . . . . . . . . . . . . . . . . . . . .
1.5 V
. . . . . . . . . . . . . . .
0 to 3.0 V
1 V/ns (20 to 80%)
Output Timing Reference Level
Output Load
. . . . . . . . . . . . . .
1.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . .
See Figure 1 Unless Otherwise Noted
READ/WRITE CYCLE TIMING
(See Notes 1, 2, 3, and 4)
63P631A–117
117 MHz
63P631A–100
100 MHz
63P631A–75
75 MHz
63P631A–66
66 MHz
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Min
Max
Unit
Notes
Cycle Time
tKHKH
tKHKL
tKLKH
tKHQV
tGLQV
tKHQX1
tKHQX2
tGLQX
tGHQZ
tKHQZ
8.5
—
10
—
13
—
15
—
ns
Clock High Pulse Width
3.4
—
4
—
5.2
—
6
—
ns
Clock Low Pulse Width
3.4
—
4
—
5.2
—
6
—
ns
Clock Access Time
—
4.5
—
4.5
—
7
—
8
ns
Output Enable to Output Valid
—
4.5
—
4.5
—
5
—
5
ns
Clock High to Output Active
0
—
0
—
0
—
0
—
ns
5
Clock High to Output Change
1.5
—
1.5
—
1.5
—
1.5
—
ns
5
Output Enable to Output Active
0
—
0
—
0
—
0
—
ns
5
Output Disable to Q High–Z
—
5.5
—
5.5
—
7
—
8
ns
5, 6
Clock High to Q High–Z
1.5
5.5
1.5
5.5
2
7
2
8
ns
5, 6
Setup Times:
Address
ADSP, ADSC,
ADV
Data In
Write
Chip Enable
tADKH
tADSKH
tDVKH
tWVKH
tEVKH
2.5
—
2.5
—
2.5
—
2.5
—
ns
Hold Times:
Address
ADSP, ADSC,
ADV
Data In
Write
Chip Enable
tKHAX
tKHADSX
tKHDX
tKHWX
tKHEX
0.5
—
0.5
—
0.5
—
0.5
—
ns
Sleep Mode Standby
tZZS
—
2 x
tKHKH
—
2 x
tKHKH
—
2 x
tKHKH
—
2 x
tKHKH
ns
Sleep Mode Recovery
tZZREC
2 x
tKHKH
—
2 x
tKHKH
—
2 x
tKHKH
—
2 x
tKHKH
—
ns
Sleep Mode High to Q High–Z
tZZQZ
—
15
—
15
—
15
—
15
ns
NOTES:
1. Write applies to all SBx, SW, and SGW signals when the chip is selected and ADSP high.
2. Chip Enable applies to all SE1, SE2 and SE3 signals whenever ADSP or ADSC is asserted.
3. All read and write cycle timings are referenced from K or G.
4. G is a don’t care after write cycle begins. To prevent bus contention, G should be negated prior to start of write cycle.
5. This parameter is sampled and is not 100% tested.
6. Measured at
±
200 mV from steady state.
OUTPUT
Z0 = 50
RL = 50
VT = 1.5 V
Figure 1. AC Test Load
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