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參數資料
| 型號： | MCM63P736ZP133R |
| 廠商： | MOTOROLA INC |
| 元件分類： | SRAM |
| 英文描述： | 128K x 36 and 256K x 18 Bit Pipelined BurstRAM Synchronous Fast Static RAM |
| 中文描述： | 128K X 36 CACHE SRAM, 4 ns, PBGA119 |
| 封裝： | PLASTIC, BGA-119 |
| 文件頁數： | 20/27頁 |
| 文件大小： | 328K |
| 代理商： | MCM63P736ZP133R |
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MCM63P636
20
MOTOROLA FAST SRAM
TAP AC OPERATING CONDITIONS AND CHARACTERISTICS
(TA = 0 to 70
°
C, Unless Otherwise Noted)
AC TEST CONDITIONS
Parameter
Value
Unit
Input Timing Reference Level
VDDQ/2
0 to 2.0
V
Input Pulse Levels
V
Input Rise/Fall Time (20 to 80%)
1
V/ns
Output Timing Reference Level
VDDQ/2
—
V
Output Load (See Figure 4 Unless Otherwise Noted)
—
TAP CONTROLLER TIMING
Parameter
Symbol
Min
Max
Unit
Notes
TCK Cycle Time
tTHTH
tTH
tTL
tTLQV
tTSRT
tCS
tDVTH
tMVTH
60
—
ns
TCK Clock High Time
25
—
ns
TCK Clock Low Time
25
—
ns
TDO Access Time
1
10
ns
TRST Pulse Width
40
—
ns
Setup Times
Capture
TDI
TMS
5
5
5
—
ns
1
Hold Times
Capture
TDI
TMS
tCH
tTHDX
tTHMX
13
14
14
—
ns
1
NOTE:
1. tCS and tCH define the minimum pauses in RAM I/O transitions to assure accurate pad data capture.
tTHDX
tTLQV
tDVTH
tTLTH
tTHMX
tMVTH
TAP CONTROLLER TIMING DIAGRAM
tTHTH
TEST CLOCK
(TCK)
TEST MODE SELECT
(TMS)
TEST DATA IN
(TDI)
TEST DATA OUT
(TDO)
tTHTL
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