- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄371087 > MCM63P818TQ100R (MOTOROLA INC) 128K x 36 and 256K x 18 Bit Pipelined BurstRAM Synchronous Fast Static RAM PDF資料下載
參數(shù)資料
| 型號(hào)： | MCM63P818TQ100R |
| 廠商： | MOTOROLA INC |
| 元件分類： | DRAM |
| 英文描述： | 128K x 36 and 256K x 18 Bit Pipelined BurstRAM Synchronous Fast Static RAM |
| 中文描述： | 256K X 18 CACHE SRAM, 5 ns, PQFP100 |
| 封裝： | TQFP-100 |
| 文件頁(yè)數(shù)： | 5/27頁(yè) |
| 文件大小： | 328K |
| 代理商： | MCM63P818TQ100R |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)當(dāng)前第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)
MCM63P636
5
MOTOROLA FAST SRAM
TQFP PIN DESCRIPTIONS
Pin Locations
Symbol
Type
Description
85
ADS
Input
Synchronous Address Status: Active low, used to initiate read or write
state machines latch in external addresses, or deselect chip.
(a) 1, 2, 3, 6, 7, 8, 9, 12, 13, 18,
19, 22, 23, 24, 25, 28, 29, 30
(b) 51, 52, 53, 56, 57, 58, 59, 62, 63,
68, 69, 72, 73, 74, 75, 78, 79, 80
DQx
I/O
Synchronous Data I/O: “x” refers to the word being read or written
(I/Os a and b).
89
K
Input
Clock: This signal registers the address, data in, and all control signals.
84
RESET
Input
Asynchronous Power–On Reset: Active low at power up, resets internal
state machines.
32, 33, 34, 35, 44, 45, 46,
47, 48, 49, 81, 82, 99, 100
SA
Input
Synchronous Address Inputs: These inputs are registered and must
meet setup and hold times.
36, 37
SA1, SA0
Input
Synchronous Address Inputs: These pins must be wired to the two
LSBs of the address bus for proper burst operation. These inputs are
registered and must meet setup and hold times.
98
SE1
Input
Synchronous Chip Enable: Active low to enable chip.
97
SE2
Input
Synchronous Chip Enable: Active high to enable chip.
92
SE3
Input
Synchronous Chip Enable: Active low to enable chip.
93
SK
Input
Data Strobe Clock: 180 degrees out–of–phase with K. Used only with
data strobes.
16
STRBA
Output
Data Strobe: Used in reference to DQa I/Os.
14
STRBA
Output
Data Strobe: Used in reference to DQa I/Os.
64
STRBB
Output
Data Strobe: Used in reference to DQb I/Os.
66
STRBB
Output
Data Strobe: Used in reference to DQb I/Os.
88
W
Input
Synchronous Write.
15, 41, 65, 91
VDD
VDDI
VDDQ
VSS
Supply
Core Power Supply.
38, 43, 87, 94
Supply
Input Power Supply.
4, 11, 20, 27, 54, 61, 70, 77
Supply
I/O Power Supply.
5, 10, 17, 21, 26, 40,
55, 60, 67, 71, 76, 90
Supply
Ground.
31, 39, 42, 50, 86
NC
—
No Connection: There is no connection to the chip.
83
NU/VDD
—
Not Usable: There is an internal connection to the chip. This pin may be
left unconnected or tied to VDD.
95, 96
NU/VSS
—
Not Usable: There is an internal connection to the chip. This pin may be
left unconnected or tied to VSS.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MCM63P818TQ133 | 128K x 36 and 256K x 18 Bit Pipelined BurstRAM Synchronous Fast Static RAM |
| MCM63P818TQ133R | 128K x 36 and 256K x 18 Bit Pipelined BurstRAM Synchronous Fast Static RAM |
| MCM63P818TQ66 | 128K x 36 and 256K x 18 Bit Pipelined BurstRAM Synchronous Fast Static RAM |
| MCM63P818TQ66R | 128K x 36 and 256K x 18 Bit Pipelined BurstRAM Synchronous Fast Static RAM |
| MCM63P818ZP66R | 128K x 36 and 256K x 18 Bit Pipelined BurstRAM Synchronous Fast Static RAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MCM63P818TQ133 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:128K x 36 and 256K x 18 Bit Pipelined BurstRAM Synchronous Fast Static RAM |
| MCM63P818TQ133R | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:128K x 36 and 256K x 18 Bit Pipelined BurstRAM Synchronous Fast Static RAM |
| MCM63P818TQ66 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:128K x 36 and 256K x 18 Bit Pipelined BurstRAM Synchronous Fast Static RAM |
| MCM63P818TQ66R | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:128K x 36 and 256K x 18 Bit Pipelined BurstRAM Synchronous Fast Static RAM |
| MCM63P818ZP100 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:128K x 36 and 256K x 18 Bit Pipelined BurstRAM Synchronous Fast Static RAM |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。