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參數資料
| 型號： | MCM64PE32SDG66 |
| 廠商： | MOTOROLA INC |
| 元件分類： | DRAM |
| 英文描述： | 256K/512K Pipelined BurstRAM Secondary Cache Module for Pentium |
| 中文描述： | 32K X 64 CACHE TAG SRAM MODULE, 8 ns, DMA160 |
| 封裝： | CARD EDGE MODULE-160 |
| 文件頁數： | 8/12頁 |
| 文件大小： | 190K |
| 代理商： | MCM64PE32SDG66 |
MCM64AF32
8
MOTOROLA FAST SRAM
DATA RAMs WRITE CYCLE
(CWE Controlled, See Notes 1 and 2)
–15
Parameter
Symbol
Min
Max
Unit
Notes
Write Cycle Time
tAVAV
tAVWL
tAVWH
tWLWH,
tWLEH
15
—
ns
3
Address Setup Time
0
—
ns
Address Valid to End of Write
12
—
ns
Write Pulse Width
12
—
ns
Write Pulse Width, COE High
tWLWH,
tWLEH
10
—
ns
4
Data Valid to End of Write
tDVWH
tWHDX
tWLQZ
tWHQX
tWHAX
7
—
ns
Data Hold Time
0
—
ns
Write Low to Output High–Z
0
7
ns
5, 6, 7
Write High to Output Active
4
—
ns
5, 6, 7
Write Recovery Time
0
—
ns
NOTES:
1. A write occurs when CWE low.
2. If COE goes low coincident with or after CWE goes low, the output will remain in a high impedance state.
3. All timings are referenced from the last valid address to the first address transition.
4. If COE
≥
VIH, the output will remain in a high impedance state.
5. At any given voltage and temperature, tWLQZ max is less than tWHQX min, both for a given device and from device to device.
6. Transition is measured
±
500 mV from steady–state voltage with load of Figure 1B.
7. This parameter is sampled and not 100% tested.
DATA RAMs WRITE CYCLE (CALE
≥
VIH)
(CWE Controlled, See Notes 1 and 2)
DATA VALID
tDVWH
tAVWL
tAVWH
tAVAV
tWHAX
tWLWH
tWHDX
tWLQZ
tWHQX
HIGH–Z
HIGH–Z
CWEx (WRITE ENABLE)
Q (DATA OUT)
D (DATA IN)
tWLEH
A5 – A17
CAAx, CABx
(CACHE ADDRESS A/B)
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相關代理商/技術參數 |
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| MCM64PE64SDG66 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:256K/512K Pipelined BurstRAM Secondary Cache Module for Pentium |
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