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參數(shù)資料
型號(hào): MCM6706BRJ6R
廠商: MOTOROLA INC
元件分類: DRAM
英文描述: 32K x 8 Bit Static Random Access Memory
中文描述: 32K X 8 STANDARD SRAM, 6 ns, PDSO32
封裝: 0.300 INCH, SOJ-32
文件頁數(shù): 1/8頁
文件大小: 151K
代理商: MCM6706BRJ6R
MCM6706R
1
Motorola, Inc. 1995
32K x 8 Bit Static Random Access
Memory
The MCM6706R is a 262,144 bit static random access memory organized as
32,768 words of 8 bits, fabricated using high performance silicon–gate BiCMOS
technology. Static design eliminates the need for external clocks or timing
strobes.
Output enable (G) is a special control feature that provides increased system
flexibility and eliminates bus contention problems.
The MCM6706R meets JEDEC standards and is available in a revolutionary
pinout 300 mil, 32–lead surface–mount SOJ package.
Single 5.0 V
±
10% Power Supply
Fully Static — No Clock or Timing Strobes Necessary
All Inputs and Outputs Are TTL Compatible
Three State Outputs
Fast Access Times: MCM6706R–6 = 6 ns
MCM6706R–7 = 7 ns
MCM6706R–8 = 8 ns
Center Power and I/O Pins for Reduced Noise
BLOCK DIAGRAM
ROW
DECODER
MEMORY
MATRIX
512 ROWS x 64 x 8
COLUMNS
INPUT
DATA
CONTROL
COLUMN I/O
COLUMN DECODER
A
A
A
A
A
A
A
A
DQ0
A
A
A
E
W
G
VCC
VSS
A
A
A
A
DQ7
Order this document
by MCM6706R/D
SEMICONDUCTOR TECHNICAL DATA
PIN ASSIGNMENT
MCM6706R
J PACKAGE
300 MIL SOJ
CASE 857–02
32
31
30
29
28
27
26
25
24
23
22
21
2
3
1
5
6
4
7
9
10
8
12
13
11
14
20
15
16
19
18
17
A1
A2
A3
E
A7
W
A4
A5
A6
VCC
VSS
A11
A9
A8
A10
DQ5
DQ6
A12
G
A13
A14
VCC
VSS
DQ1
DQ3
A0
NC
NC
DQ0
DQ2
DQ4
DQ7
A0 – A14
W
. . . . . . . . . . . . . . . . . . . .
E
. . . . . . . . . . . . . . . . . . . . . .
G
. . . . . . . . . . . . . . . . . . .
DQ0 – DQ7
. . . . . . . .
VCC
. . . . . . . . . . . .
VSS
. . . . . . . . . . . . . . . . . . . . . . .
NC
. . . . . . . . . . . . . . . . .
Address
. . . . . . . . . . . . . . . . . .
Write Enable
Chip Enable
Output Enable
Data Input/Output
+ 5 V Power Supply
Ground
No Connection
PIN NAMES
REV 1
5/95
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