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參數資料
| 型號： | MCM67A618A |
| 廠商： | Motorola, Inc. |
| 英文描述： | 64K x 18 Bit Asynchronous/Latched Address Fast Static RAM(64K x 18位異步/鎖存地址快速靜態RAM) |
| 中文描述： | 64K的× 18位異步/鎖存地址快速靜態存儲器（64K的× 18位異步/鎖存地址快速靜態內存） |
| 文件頁數： | 1/12頁 |
| 文件大?。?/td> | 143K |
| 代理商： | MCM67A618A |
MCM67A618A
1
Motorola, Inc. 1996
64K x 18 Bit Asynchronous/
Latched Address Fast Static RAM
The MCM67A618A is a 1,179,648 bit latched address static random access
memory organized as 65,536 words of 18 bits. The device integrates a 64K x 18
SRAM core with advanced peripheral circuitry consisting of address and data in-
put latches, active low chip enable, separate upper and lower byte write strobes,
and a fast output enable. This device has increased output drive capability sup-
ported by multiple power pins.
Address, data in, and chip enable latches are provided. When latch enables
(AL for address and chip enables and DL for data in) are high, the address, data
in, and chip enable latches are in the transparent state. If latch enables are tied
high the device can be used as an asynchronous SRAM. When latch enables are
low the address, data in, and chip enable latches are in the latched state. This
input latch simplifies read and write cycles by guaranteeing address and data–in
hold time in a simple fashion.
Dual write enables (LW and UW) are provided to allow individually
writeable bytes. LW controls DQ0 – DQ8 (the lower bits) while UW
controls DQ9 – DQ17 (the upper bits).
Six pair of power and ground pins have been utilized and placed on
the package for maximum performance.
The MCM67A618A will be available in a 52–pin plastic leaded chip
carrier (PLCC).
This device is ideally suited for systems that require wide data bus
widths, cache memory, and tag RAMs.
Single 5 V
±
5% Power Supply
Fast Access Times: 10/12/15 ns Max
Byte Writeable via Dual Write Enables
Separate Data Input Latch for Simplified Write Cycles
Address and Chip Enable Input Latches
Common Data Inputs and Data Outputs
Output Enable Controlled Three–State Outputs
3.3 V I/O Compatible
High Board Density 52–Lead PLCC Package
PIN ASSIGNMENT
VCC
VSS
DQ11
DQ12
DQ13
DQ14
VSS
VCC
DQ15
DQ16
DQ17
DQ10
DQ9
DQ7
DQ6
VCC
VSS
DQ5
DQ4
DQ3
DQ2
VSS
VCC
DQ1
DQ0
8
9
10
11
12
13
14
15
16
17
18
19
20
46
45
44
43
42
41
40
39
38
37
36
35
34
47
48
49
50
51
52
1
2
3
4
5
6
7
33
32
31
30
29
28
27
26
25
24
23
22
21
S
V
DQ8
C
V
A
A
A
A
A
A
A
A
A
A
A
V
V
A
A
A
A
G
A
A
E
U
L
D
All power supply and ground pins must be con-
nected for proper operation of the device.
PIN NAMES
A0 – A15
AL
. . . . . . . . . . . . . . . . . . . . . .
DL
. . . . . . . . . . . . . . . . . . . . . . . . .
LW
. . . . . . . . . . . .
UW
. . . . . . . . . . . .
E
. . . . . . . . . . . . . . . . . . . . . . . . .
G
. . . . . . . . . . . . . . . . . . . . . .
DQ0 – DQ17
. . . . . . . . . . .
VCC
. . . . . . . . . . . . . . . .
VSS
. . . . . . . . . . . . . . . . . . . . . . . . . . .
Address Inputs
Address Latch
Data Latch
. . . . . . . . . . . . . . . .
Lower Byte Write Enable
Higher Byte Write Enable
Chip Enable
Output Enable
Data Input/Output
+ 5 V Power Supply
Ground
Order this document
by MCM67A618A/D
SEMICONDUCTOR TECHNICAL DATA
MCM67A618A
FN PACKAGE
PLASTIC
CASE 778–02
REV 1
10/9/96
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相關代理商/技術參數 |
參數描述 |
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| MCM67A618B | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:64K x 18 Bit Asynchronous/ Latched Address Fast Static RAM |
| MCM67A618BFN10 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:64K x 18 Bit Asynchronous/ Latched Address Fast Static RAM |
| MCM67A618BFN12 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:64K x 18 Bit Asynchronous/ Latched Address Fast Static RAM |
| MCM67A618BFN15 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:64K x 18 Bit Asynchronous/ Latched Address Fast Static RAM |
| MCM67A618FN10 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:64K x 18 Bit Asychronous/Latched Address Fast Static RAM |
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