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參數(shù)資料
| 型號： | MCM69L736AZP10.5 |
| 廠商： | MOTOROLA INC |
| 元件分類： | DRAM |
| 英文描述： | 4M Late Write HSTL |
| 中文描述： | 128K X 36 CACHE SRAM, 10.5 ns, PBGA119 |
| 封裝： | 14 X 22 MM, 1.27 MM PITCH, PLASTIC, BGA-119 |
| 文件頁數(shù)： | 1/20頁 |
| 文件大小： | 225K |
| 代理商： | MCM69L736AZP10.5 |
MCM69L736A
MCM69L818A
1
Motorola, Inc. 1997
Advance Information
4M Late Write HSTL
The MCM69L736A/818A is a 4M synchronous late write fast static RAM
designed to provide high performance in secondary cache and ATM switch,
Telecom, and other high speed memory applications. The MCM69L818A
(organized as 256K words by 18 bits) and the MCM69L736A (organized as 128K
words by 36 bits) are fabricated in Motorola’s high performance silicon gate
BiCMOS technology.
The differential clock (CK) inputs control the timing of read/write operations of
the RAM. At the rising edge of CK, all addresses, write enables, and synchronous
selects are registered. An internal buffer and special logic enable the memory to
accept write data on the rising edge of CK a cycle after address and control
signals. Read data is available at the falling edge of CK.
The RAM uses HSTL inputs and outputs. The adjustable input trip–point (Vref)
and output voltage (VDDQ) gives the system designer greater flexibility in
optimizing system performance.
The synchronous write and byte enables allow writing to individual bytes or the
entire word.
The impedance of the output buffers is programmable, allowing the outputs to
match the impedance of the circuit traces which reduces signal reflections.
Byte Write Control
Single 3.3 V +10%, – 5% Operation
HSTL — I/O (JEDEC Standard JESD8–6 Class I)
HSTL — User Selectable Input Trip–Point
HSTL — Compatible Programmable Impedance Output Drivers
Register to Latch Synchronous Operation
Asynchronous Output Enable
Boundary Scan (JTAG) IEEE 1149.1 Compatible
Differential Clock Inputs
Optional x18 or x36 Organization
MCM69L736A/818A–7.5 = 7.5 ns
MCM69L736A/818A–8.5 = 8.5 ns
MCM69L736A/818A–9.5 = 9.5 ns
MCM69L736A/818A–10.5 = 10.5 ns
119 Bump, 50 mil (1.27 mm) Pitch, 14 mm x 22 mm Plastic Ball Grid Array
(PBGA) Package
This document contains information on a new product. Specifications and information herein are subject to change without notice.
Order this document
by MCM69L736A/D
SEMICONDUCTOR TECHNICAL DATA
MCM69L736A
MCM69L818A
ZP PACKAGE
PBGA
CASE 999–01
4/3/97
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MCM69L818AZP10.5 | ER 23C 16 12 8 4 SKT PLUG |
| MCM69L736AZP10.5R | 4M Late Write HSTL |
| MCM69L818AZP10.5R | 4M Late Write HSTL |
| MCM69L736AZP9.5 | Circular Connector; MIL SPEC:MIL-C-26482, Series I, Solder; Body Material:Aluminum; Series:PT06; Number of Contacts:4; Connector Shell Size:8; Connecting Termination:Solder; Circular Shell Style:Straight Plug; Body Style:Straight |
| MCM69L818AZP9.5 | Circular Connector; MIL SPEC:MIL-C-26482, Series I, Solder; Body Material:Aluminum; Series:PT06; Connector Shell Size:8; Connecting Termination:Solder; Circular Shell Style:Straight Plug; Body Style:Straight |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MCM69L736AZP7.5 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:4M Late Write HSTL |
| MCM69L736AZP7.5R | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:4M Late Write HSTL |
| MCM69L736AZP8.5 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:4M Late Write HSTL |
| MCM69L736AZP8.5R | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:4M Late Write HSTL |
| MCM69L736AZP9.5 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:4M Late Write HSTL |
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