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參數資料
| 型號： | MCTSD01-V100 |
| 廠商： | Lineage Power |
| 英文描述： | SDRAM Controller(同步動態RAM控制器) |
| 中文描述： | SDRAM控制器（同步動態內存控制器） |
| 文件頁數： | 1/12頁 |
| 文件大小： | 417K |
| 代理商： | MCTSD01-V100 |
Features
-
Single-chip SDRAM controller in a ORCA 2TA or 3C/T FPGA
-
Designed for high speed and high performance applications
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Up to 355 Mbytes/s in 64 bit
-
CPU independent
-
Support for burst mode
-
Utilizes auto refresh mode
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SDRAM available in Self-Refresh mode (SDRAM dependant)
-
Supports multiple 16-Mbit SDRAM types
-
Handles Complexity of SDRAM
-
Available in source code format for ease of customization
-
Can be customized by Logic Design Solutions or by the customer
General Description
The function of the macro SDRAM controller, implemented on a ORCA FPGA, is to connect microprocessor to a bank of
SDRAM memory.
This macro can be customized according to your specific needs (microprocessor and application specific requirement).
The arbiter and decoding logic can be integrated in the FPGA in addition to any other pre-designed functions.
FPGA density and I/O requirements are defined according to customer specification.
Design Package
Device Family
PFUs
I/O
Product
2TA - 3C/T
80 (2TA) – 25 (3C/T) *
60
**
MCTSD01_V100
: 100 MHz – CAS Latency = 3 –
ORCA 2TA-7 / 3T-6
VHDL Source code
VHDL Test Bench
for behavioral and gate level simulation.
Data Sheet
Design Document
:
features, architecture, interfaces and operation.
User’s guide :
simulation, synthesis and Place and route procedures.
.prf file
VHDL synthesis Leonardo Spectrum from Exemplar.
VHDL simulation tool.
ORCA Foundry from Lucent.
Support provided by Logic Design Solutions 90 days e-mail and telephone support
from Logic Design Solutions included in the Macro price. Support does not cover user
Macro modifications. Maintenance Contracts available.
Documentation
Constraint Files
Design Tool Requirement
Support
* Rounded number.
** Assuming all Macro signals are routed off chip.
Data Sheet
Jan. 99 – Ver. 1
MCTSD01-V100
SDRAM Controller
MACRO
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