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參數資料
| 型號： | MCZ34652EFR2 |
| 廠商： | Freescale Semiconductor |
| 文件頁數： | 17/26頁 |
| 文件大小： | 1802K |
| 描述： | IC HOTSWAP CTRLR 2A NEG 16SOIC |
| 標準包裝： | 2,500 |
| 類型： | 熱交換開關 |
| 應用： | 通用 |
| 內部開關： | 是 |
| 電流限制： | 2A |
| 電源電壓： | 15 V ~ 80 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.154"，3.90mm 寬） |
| 供應商設備封裝： | 16-SOIC N |
| 包裝： | 帶卷 (TR) |
Analog Integrated Circuit Device Data
Freescale Semiconductor
17
34652
FUNCTIONAL DEVICE OPERATION
PROTECTION FEATURES
rchived by Freescale Semiconductor, Inc., 2008
The power dissipation in the device can be calculated as
follows:
P = I
2
(LOAD)
*
R
DS(ON)
OR
P = [T
J
(max) - T
A
(max)] / R
窲A
Combining the two equations:
I
2
(LOAD)
= [ T
J
(max) - T
A
(max)] / [R
窲A
*
R
DS(ON)
] Eq 1
For example:
T
A
(max) = 55癈
R
窲A
= 51癈/W for a four-layer board
R
DS(ON)
= 0.251 ?at high temperatures
Then:
I
2
(LOAD)
= [ T
J
(max) - 55癈] / [51癈/W
*
0.251
I
2
(LOAD)
= [ T
J
(max) - 55癈] / 12.80癈 / A
2
So if the overcurrent limit is 2.0 A, then the maximum
junction temperature is 106.2癈, which is well below the
thermal shutdown temperature that is allowed.
The previous explanation applies to steady state power
when the device is in normal operation. During the charging
process, the power is dominated by the I * V across the Power
MOSFET. When charging starts, the power in the Power
MOSFET rises up and reaches a maximum value of I * V, then
quickly ramps back down to the steady state level in a period
governed by the size of the loads input capacitor that is being
charged and by the value of the charging current limit I
CHG
.
In this case the instantaneous power dissipation is much
higher than the steady state case, but it is on for a very short
time.
For example:
I
CHG
= 100 mA, the default value
C
LOAD
= 400 ?/SPAN>F, a very large capacitor
V
PWR
= 80 V, worst case
Then:
The power pulse magnitude = I
CHG
*
V
PWR
= 8.0 W
The power pulse duration = C
LOAD
*
V
PWR
/ I
CHG
= 320 ms
Figure 17
displays the temperature profile of the device
under the instantaneous power pulse during the charging
process. Table 5
depicts thermal resistance values for
different board configurations.
Figure 17. Instantaneous Temperature Rise of an 8.0 W
0.0
10.0
20.0
30.0
40.0
50.0
60.0
0
100
200
300
400
Time (millisec)
Time (ms)
Table 5. Thermal Resistance Data
Type
Condition
Symbol Value Unit
Junction to Ambient
Single-layer board (1s), per JEDEC JESD51-2 with board (JESD51-3) horizontal
R
?/DIV>
JA
103 癈/W
Junction to Ambient
Four-layer board (2s2p), per JEDEC JESD51-2 with board (JESD51-3) horizontal
R
?/DIV>
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JMA
65 癈/W
Junction to Ambient
Single-layer board with a 300 mm
2
radiator pad on its top surface, not standard JEDEC
69 癈/W
Junction to Ambient
Single-layer board with a 600 mm
2
radiator pad on its top surface, not standard JEDEC
65 癈/W
Junction to Ambient
Four-layer board with a via for each thermal lead, not standard JEDEC
51 癈/W
Junction to Ambient
Four-layer board with a 300 mm
2
radiator pad on its top surface and a full array of vias
between radiator pad and top surface, not standard JEDEC
47 癈/W
Junction to Ambient
Four-layer board with a 600 mm
2
radiator pad on its top surface and a full array of vias
between radiator pad and top surface, not standard JEDEC
47 癈/W
Junction to Board
Thermal resistance between die and board per JEDEC JESD51-8
R
?/DIV>
JB
29 癈/W
Junction to Case
Thermal resistance between die and case top
R
?/DIV>
JC
33 癈/W
Junction to Package
Top
Temperature difference between package top and junction per JEDEC JESD51-2
?/DIV>
JT
12 癈/W
Junction to Lead
Thermal resistance between junction and thermal lead, not standard JEDEC
R
?/DIV>
JL
33 癈/W
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