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參數(shù)資料
| 型號(hào)： | MH1S72CPG-15 |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | 75497472-BIT (1048576-WORD BY 72-BIT)SynchronousDRAM |
| 中文描述： | 75497472位（1048576 - Word的72位）SynchronousDRAM |
| 文件頁數(shù)： | 1/47頁 |
| 文件大小： | 681K |
| 代理商： | MH1S72CPG-15 |
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MH1S72CPG-10,-12,-15
75497472-BIT (1048576-WORD BY 72-BIT)SynchronousDRAM
MITSUBISHI LSIs
( / 47 )
1
MITSUBISHI
ELECTRIC
28.Mar.1997
Preliminary Spec.
Some contents are subject to change without notice.
MIT-DS-0089-3.0
DESCRIPTION
The MH1S72CPG is 1048576-word by 64-bit
Synchronous DRAM module. This consists of five
industry standard 1Mx16 Synchronous DRAMs in
TSOP and one industory standard EEPROM in
TSSOP.
The mounting of TSOP on a card edge Dual Inline
package provides any application where high
densities and large quantities of memory are
required.
This is a socket type - memory modules, suitable for
easy interchange or addition of modules.
FEATURES
Clock frequency 100MHz/83MHz/67MHz
single 3.3V±0.3V power supply
Fully synchronous operation referenced to clock rising
edge
Burst length- 1/2/4/8(programmable)
Dual bank operation controlled by BA(Bank Address)
/CAS latency- 1/2/3(programmable)
APPLICATION
main memory or graphic memory in computer systems
Auto precharge / All bank precharge controlled by A10
Burst type- sequential / interleave(programmable)
Column access - random
LVTTL Interface
Auto refresh and Self refresh
4096 refresh cycle /64ms
1pin
10pin
11pin
40pin
41pin
84pin
F
85pin
94pin
95pin
124pin
125pin
168pin
B
Utilizes industry standard 1M x 16 Synchronous DRAMs
TSOP and industry standard EEPROM in TSSOP
168-pin (84-pin dual in-line package)
Frequency
-15
67MHz
CLK Access Time
(Component SDRAM)
9ns (CL=3)
-10
100MHz
8ns(CL=3)
-12
83MHz
8ns (CL=3)
Module item "-10","-12" , and "-15" show mounted SDRAM devices Cycle time(min.).
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