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參數資料
| 型號： | MH64D64AKQH-75 |
| 廠商： | Mitsubishi Electric Corporation |
| 元件分類： | 圓形連接器 |
| 英文描述： | Circular Connector; No. of Contacts:128; Series:MS27484; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:24; Circular Contact Gender:Pin; Circular Shell Style:Straight Plug; Insert Arrangement:24-35 RoHS Compliant: No |
| 中文描述： | 4294967296位（67108864字64位），雙數據速率同步DRAM模塊 |
| 文件頁數： | 1/40頁 |
| 文件大小： | 362K |
| 代理商： | MH64D64AKQH-75 |
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MH64D64AKQH-75,-10
4,294,967,296-BIT (67,108,864-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
MIT-DS-0418-0.1
17.May.2001
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MITSUBISHI
ELECTRIC
1
DESCRIPTION
APPLICATION
Main memory unit for Note PC, Mobile etc.
FEATURES
Type name
133MHz
MH64D64AKQH-10
MH64D64AKQH-75
Max.
Frequency
100MHz
The MH64D64AKQH is 67108864 - word x 64-bit Double
Data Rate(DDR) Synchronous DRAM mounted module.
This consists of 16 industry standard 32M x 8 DDR
Synchronous DRAMs in Small TSOP with SSTL_2 interface
which achieves very high speed data rate up to 133MHz.
This socket-type memory module is suitable for main
memory in computer systems and easy to interchange or
add modules.
CLK
Access Time
[component level]
+ 0.75ns
+ 0.8ns
(Front)
(Back)
1
2
199
200
PCB Outline
-
Utilizes industry standard 32M X 8 DDR Synchronous DRAMs
in Smal TSOP package , industry standard EEPROM(SPD) in
TSSOP package
-
200pin SO-DIMM
-
Vdd=Vddq=2.5v±0.2V
- Double data rate architecture; two data transfers per
clock cycle
- Bidirectional, data strobe (DQS) is transmitted/received
with data
- Differential clock inputs (CLK and /CLK)
-
DLL aligns DQ and DQS transitions with CLK transition edges of DQS
- Commands entered on each positive CLK edge
- Data and data mask referenced to both edges of DQS
- 4bank operation concontrolled byBA0,BA1(Bank Address
,discrete)
- /CAS latency- 2.0/2.5 (programmable)
- Burst length- 2/4/8 (programmable)
- Burst Type - sequential/interleave(programmable)
- Auto precharge / All bank precharge controlled by A10
- 8192 refresh cycles /64ms
- Auto refresh and Self refresh
- Row address A0-12 / Column address A0-9
- SSTL_2 Interface
- Module 2bank Configration
相關PDF資料 |
PDF描述 |
|---|---|
| MH88422BD-1 | Data Access Arrangement Preliminary Information |
| MH88422 | Line Interface Circuit Preliminary Information |
| MH88422-1 | Data Access Arrangement Preliminary Information |
| MH88422-2 | Data Access Arrangement Preliminary Information |
| MH88422-3 | Data Access Arrangement Preliminary Information |
相關代理商/技術參數 |
參數描述 |
|---|---|
| MH64D72KLG-10 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:4,831,838,208-BIT (67,108,864-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module |
| MH64D72KLG-75 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:4,831,838,208-BIT (67,108,864-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module |
| MH64D72KLH-10 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:4,831,838,208-BIT (67,108,864-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module |
| MH64D72KLH-75 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:4,831,838,208-BIT (67,108,864-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module |
| MH64FAD | 制造商:MTRONPTI 制造商全稱:MTRONPTI 功能描述:8 pin DIP, 3.3 or 5.0 Volt, HCMOS/TTL Clock Oscillator |
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