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參數資料
| 型號： | MH8V725BAZTJ-6 |
| 廠商： | Mitsubishi Electric Corporation |
| 元件分類： | 圓形連接器 |
| 英文描述： | Circular Connector; Body Material:Aluminum; Series:PT00; No. of Contacts:3; Connector Shell Size:14; Connecting Termination:Solder; Circular Shell Style:Wall Mount Receptacle; Circular Contact Gender:Socket; Insert Arrangement:14-91 |
| 中文描述： | 超頁模式603979776 -位（8388608 - Word的72 -位）動態隨機存儲器 |
| 文件頁數： | 1/23頁 |
| 文件大小： | 147K |
| 代理商： | MH8V725BAZTJ-6 |
MITSUBISHI LSIs
MH8V725BAZTJ -5, -6
Preliminary Spec.
Specifications subject to
change without notice.
MITSUBISHI
ELECTRIC
( / 23 )
1
9/Nov. /1998
HYPER PAGE MODE 603979776 - BIT ( 8388608 - WORD BY 72 - BIT ) DYNAMIC RAM
MIT-DS-0285-0.0
DESCRIPTION
The MH8V725BAZTJ is 8388608-word x 72-bit dynamic
ram module. This consist of nine industry standard 8M x 8
dynamic RAMs in TSOP and three industry standard input
buffer in TSSOP.
The mounting of TSOP on a card edge dual in-line package
provides any application where high densities and large of
quantities memory are required.
This is a socket-type memory module ,suitable for easy
interchange or addition of module.
FEATURES
/RAS
access
time
(max.ns)
(max.ns)
MH8V725BAZTJ-5
Type name
/CAS
access
time
Address
access
time
(max.ns)
/OE
access
time
(max.ns)
Cycle
Power
time
(min.ns)
dissipation
(typ.W)
50
60
18
20
30
35
18
20
90
110
Utilizes industry standard 8M x 8 RAMs in TSOP and industry
standard input buffer in TSSOP
168-pin (84-pin dual dual in-line package)
Single +3.3V(±0.3V) supply operation
Low stand-by power dissipation
116.2mW(Max) . . . . . . . . . . LVCMOS input level
Low operation power dissipation
MH8V725BAZTJ -5 . . . . . . . . . . . . . . . . . . 3.34W(Max)
MH8V725BAZTJ -6 . . . . . . . . . . . . . . . . . . 3.02W(Max)
All input are directly LVTTL compatible
All output are three-state and directly LVTTL compatible
Includes(0.22uF x 11) decoupling capacitors
4096 refresh cycle every 64ms (A0~12)
Hyper-page mode,Read-modify-write,
/CAS before /RAS refresh,Hidden refresh capabilities
JEDEC standard pin configuration & Buffered PD pin
Buffered input except /RAS and DQ
Gold plating contact pads
APPLICATION
Main memory unit for computers , Microcomputer memory
PD&ID TABLE
PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8 ID0
1
0
1
1
1
1
0
1
1
1
ID1
0
0
- 6
- 5
1 = NC , 0 = drive to VOL
PD pin . . . buffered. When /PDE is low, PD information can be read
ID pin . . . non-buffered
0
1
0
1
0
0
0
0
2.80
2.35
PIN CONFIGURATION
1pin
10pin
11pin
40pin
41pin
84pin
85pin
94pin
95pin
124pin
125pin
168pin
FRONT SIDE
BACK SIDE
MH8V725BAZTJ-6
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