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參數(shù)資料
| 型號： | MIC2800-GFSYML TR |
| 廠商： | Micrel Inc |
| 文件頁數(shù)： | 17/20頁 |
| 文件大小： | 506K |
| 描述： | IC REG TRPL BUCK/LINEAR 16MLF |
| 標(biāo)準(zhǔn)包裝： | 5,000 |
| 拓?fù)洌?/td> | 降壓（降壓）（1），線性（LDO）（2） |
| 功能： | 任何功能 |
| 輸出數(shù)： | 3 |
| 頻率 - 開關(guān)： | 2MHz |
| 電壓/電流 - 輸出 1： | 1.8V，600mA |
| 電壓/電流 - 輸出 2： | 1.5V，300mA |
| 電壓/電流 - 輸出 3： | 3.3V，300mA |
| 帶 LED 驅(qū)動器： | 無 |
| 帶監(jiān)控器： | 無 |
| 帶序列發(fā)生器： | 無 |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-VFQFN，16-MLF? |
| 供應(yīng)商設(shè)備封裝： | 16-MLF?（4x4） |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | MIC2800-GFSYMLTR MIC2800-GFSYMLTR-ND |
Micrel, Inc.
MIC2800
September 2007
17
M9999-090507-C
Application Notes
The MIC2800 is a digital power management IC with a
single integrated buck regulator and two independent
low dropout regulators. LDO1 is a 300mA low dropout
regulator that is using power supplied by the on board
buck regulator. LDO2 is a 300mA low dropout regulator
using the supply from the input pin. The buck regulator is
a 600mA PWM power supply that utilizes a /LOWQ light
load mode to maximize battery efficiency in light load
conditions. This is achieved with a /LOWQ control pin
that when pulled low, shuts down all the biasing and
drive current for the PWM regulator, drawing only 20礎(chǔ)
of operating current. This allows the output to be
regulated through the LDO output, capable of providing
60mA of output current. This method has the advantage
of producing a clean, low current, ultra low noise output
in /LOWQ mode. During /LOWQ mode, the SW node
becomes high impedance, blocking current flow. Other
methods of reducing quiescent current, such as pulse
frequency modulation (PFM) or bursting techniques
create large amplitude, low frequency ripple voltages
that can be detrimental to system operation.
When more than 60mA is required, the /LOWQ pin can
be forced high, causing the MIC2800 to enter PWM
mode. In this case, the LDO output makes a "hand-off"
to the PWM regulator with virtually no variation in output
voltage. The LDO output then turns off allowing up to
600mA of current to be efficiently supplied through the
PWM output to the load.
VIN
Two input voltage pins provide power to the switch mode
regular and LDO2 separately. The LDO1 input voltage is
provided by the DC/DC LDO pin. VIN provides power to
the LDO section and the bias through an internal 6&
resistor. Both VIN pins must be tied together.
For the switch mode regulator VIN provides power to the
MOSFET along with current limiting sensing. Due to the
high switching speeds, a 4.7礔 capacitor is
recommended close to VIN and the power ground
(PGND) pin for bypassing. Please refer to layout
recommendations.
LDO
The LDO pin is the output of the linear regulator and
should be connected to the output. In /LOWQ mode
(/LOWQ <0.2V), the LDO provides the output voltage. In
PWM mode (/LOWQ >1V) the LDO pin provides power
to LDO1.
LDO1
Regulated output voltage of LDO1. Power is provided by
the DCDC switching regulator. Recommended output
capacitance is 2.2礔.
LDO2
Regulated output voltage of LDO2. Power is provided by
VIN. Recommended output capacitance is 2.2礔.
EN
Both enable inputs are active high, requiring 1.0V for
guaranteed operation. EN1 provides logic control of both
the DCDC regulator and LDO1. EN2 provides logic
control for LDO2 only. The enable inputs are CMOS
logic and cannot be left floating.
The enable pins provide logic level control of the
specified outputs. When both enable pins are in the off
state, supply current of the device is greatly reduced
(typically <1礎(chǔ)). When the DCDC regulator is in the off
state, the output drive is placed in a "tri-stated" condition,
where both the high side P-channel MOSFET and the
low-side N-channel are in an off or non-conducting
state. Do not drive either of the enable pins above the
supply voltage.
Power-On Reset (POR)
The power-on reset output is an open-drain N-Channel
device, requiring a pull-up resistor to either the input
voltage or output voltage for proper voltage levels. The
POR output has a delay time that is programmable with
a capacitor from the CSET pin to ground. The delay time
can be programmed to be as long as 1 second.
/LOWQ
The /LOWQ pin provides a logic level control between
the internal PWM mode and the low noise linear
regulator mode. With /LOWQ pulled low (<0.2V),
quiescent current of the device is greatly reduced by
switching to a low noise linear regulator mode that has a
typical IQ of 20礎(chǔ). In linear (LDO) mode the output can
deliver 60mA of current to the output. By placing /LOWQ
high (>1V), the device transitions into a constant
frequency PWM buck regulator mode. This allows the
device the ability to efficiently deliver up to 600mA of
output current at the same output voltage.
/LOWQ mode also limits the output load of both LDO1
and LDO2 to 10mA.
BIAS
The BIAS pin supplies the power to the internal control
and reference circuitry. The bias is powered from AVIN
through an internal 6& resistor. A small 0.1礔 capacitor
is recommended for bypassing.
FB
Connect the feedback pin to VOUT.
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