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參數資料
| 型號： | MK2049-45SI |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數： | 1/10頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLK PLL COMM 3.3V 20-SOIC |
| 產品變化通告： | Product Discontinuation 13/May/2009 |
| 標準包裝： | 37 |
| 類型： | PLL 時鐘合成器 |
| PLL： | 是 |
| 輸入： | 時鐘 |
| 輸出： | 時鐘 |
| 電路數： | 1 |
| 比率 - 輸入:輸出： | 1:3 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 51.84MHz |
| 除法器/乘法器： | 是/是 |
| 電源電壓： | 3.15 V ~ 3.45 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-SOIC（0.295"，7.50mm 寬） |
| 供應商設備封裝： | 20-SOIC |
| 包裝： | 管件 |
DATASHEET
3.3 VOLT COMMUNICATIONS CLOCK PLL
MK2049-45
IDT / ICS 3.3 VOLT COMMUNICATIONS CLOCK PLL
1
MK2049-45
REV G 101904
Description
The MK2049-45 is a dual Phase-Locked Loop (PLL) device
which can provide frequency synthesis and jitter
attenuation. The first PLL is VCXO based and uses a
pullable crystal to track signal wander and attenuate input
jitter. The second PLL is a translator for frequency
multiplication. Basic configuration is determined by a
Mode/Frequency Selection Table. Loop bandwidth and
damping factor are programmable via external loop filter
component selection.
Buffer Mode accepts a 10 to 50MHz input and will provide a
jitter attenuated output at 0.5 x ICLK, 1 x ICLK or 2 x ICLK.
In this mode the MK2049-45 is ideal for filtering jitter from
high frequency clocks.
In External Mode, ICLK accepts an 8 kHz clock and will
produce output frequencies from a table of common
communciations clock rates, CLK and CLK/2. This allows
for the generation of clocks frequency-locked to an 8 kHz
backplane clock, simplifying clock synchronization in
communications systems.
The MK2049-45 can be dynamically switched between T1,
E1, T3, E3 outputs with the same 24.576 MHz crystal.
ICS can customize these devices for many other different
frequencies. Contact your ICS representative for more
details.
Features
Packaged in 20 pin SOIC
3.3 V + 5% operation
Meets the TR62411, ETS300 011, and GR-1244
specification for MTIE, Pull-in/Hold-in Range, Phase
Transients, and Jitter Generation for Stratum 3, 4, and 4E
Accepts multiple inputs: 8 kHz backplane clock, or 10 to
50 MHz
Locks to 8 kHz + 100 ppm (External mode)
Buffer Mode allows jitter attenuation of 10 - 50 MHz input
and x1 / x0.5 or x1 / x2 outputs
Exact internal ratios enable zero ppm error
Output rates include T1, E1, T3, E3, and OC3
submultiples
Available in Pb (lead) free package
See also the MK2049-34 and MK2049-36
Not recommended for new designs. Use the
MK2049-45A.
Block Diagram
Charge
Pump
VCXO
X2
X1
ISET
CAP2
Feedback
Divider (N)
Reference
Divider
(used in buffer
mode only)
ICLK
Reference
Divider
Phase
Detector
VCXO
PLL
Feedback
Divider
VCO
Translator
PLL
CLK
CAP1
Output
Divider
Divide
by 2
CLK/2
8k
R
S
R
SET
C
P
C
S
Optional Crystal Load Caps
Divider Value
Look-up Table
FS3:0
4
C
L
C
L
External Pullable Crystal
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相關代理商/技術參數 |
參數描述 |
|---|---|
| MK2049-45SILF | 功能描述:時鐘合成器/抖動清除器 3.3 VOLT COMMUNICA. CLOCK VCXO PLL RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| MK2049-45SILFTR | 功能描述:時鐘合成器/抖動清除器 3.3 VOLT COMMUNICA. CLOCK VCXO PLL RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| MK2049-45SITR | 功能描述:IC CLK PLL COMM 3.3V 20-SOIC RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發生器，PLL，頻率合成器 系列:- 標準包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數:1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應商設備封裝:* 包裝:* |
| MK205/100G | 制造商:Fischer Elektronik GmbH & Co KG 功能描述:Bulk |
| MK2058-01 | 制造商:ICS 制造商全稱:ICS 功能描述:Communications Clock Jitter Attenuator |
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