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參數資料
| 型號： | MK2069-01GILFTR |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數： | 1/21頁 |
| 文件大小： | 0K |
| 描述： | IC VCXO CLK SYNCHRONIZER 56TSSOP |
| 標準包裝： | 1,000 |
| 類型： | 時鐘同步器 |
| PLL： | 是 |
| 輸入： | LVCMOS |
| 輸出： | LVCMOS |
| 電路數： | 1 |
| 比率 - 輸入:輸出： | 3:3 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 160MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3.15 V ~ 3.45 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 56-TFSOP（0.240"，6.10mm 寬） |
| 供應商設備封裝： | 56-TSSOP |
| 包裝： | 帶卷 (TR) |
DATASHEET
VCXO-BASED LINE CARD CLOCK SYNCHRONIZER
MK2069-01
IDT VCXO-BASED LINE CARD CLOCK SYNCHRONIZER
1
MK2069-01
REV K 051310
Description
The MK2069-01 is a VCXO (Voltage Controlled Crystal
Oscillator) based clock generator that offers system
synchronization, jitter attenuation, and frequency
multiplication or translation. It can accept an unstable, jittery
input clock and provide a de-jittered, low phase noise
output clock at a user determined frequency. The device’s
clock multiplication ratios are user selectable since all major
PLL divider blocks can be configured through device pin
settings. External PLL loop filter components allow tailoring
of the VCXO PLL loop response and therefore the clock
jitter attenuation characteristics.
The MK2069-01 is ideal for line card applications. Its three
input MUX enables selection of the master or slave
(backup) system clocks, as well as a backup local line card
clock. The lock detector (LD) output serves as a clock
status monitor. The clear (CLR) input enables rapid
synchronization to the phase of a newly selected input
clock, while eliminating the generation of extra clock cycles
and wander caused by memory in the PLL feedback divider.
CLR also serves as a temporary holdover function when
kept low.
Features
Input clock frequency of 1 kHz to 170 MHz
Output clock frequency of 500 kHz to 160 MHz
Jitter attenuation of input clock provided by VCXO circuit.
Jitter transfer characteristics user configured through
selection of external loop filter components.
3:1 Input MUX for input reference clocks
PLL lock status output
PLL Clear function allows seamless synchronizing to an
altered input clock phase, virtually eliminating the
generation of wander or extra clock cycles.
VCXO-based clock generation offers very low jitter and
phase noise generation, even with a low frequency or
jittery input clock.
2nd PLL provides translation of VCXO PLL output
(VCLK) to higher or alternate clock frequencies (TCLK).
Device will free-run in the absence of an input clock
based on the VCXO crystal frequency.
56 pin TSSOP package
Single 3.3 V power supply
5 V tolerant inputs on ICLK0 and ICLK1
Block Diagram
C harge
Pum p
VC XO
P u lla b le
xtal
VC LK
X2
X1
ISET
4
VD D
4
CL R
LF
FV D iv ide r
1-4096
RV
Div id e r
1 ,2,4,1 2 8
SV
Div id e r
1,2 ,4,6,8,
10,12,16
IC L K 2
IC L K 1
MX 1 :0
0X
RV 1 :0
2
RT
Div id e r
1-4
Ph ase
De te cto r
VC XO
PLL
FT D iv ide r
1-64
ST
Div id e r
2,4 ,8,1 6
VC O
T ran slato r
PL L
SV 2 :0
3
F V 11:0
FT5 :0
6
ST1 :0
2
TC LK
OE V
OE T
IC L K 0
10
01
2
LD
OE L
GN D
RCL K
OE R
Lo c k D e tector
12
LD C
LD R
LF R
RT 1 :0
2
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相關代理商/技術參數 |
參數描述 |
|---|---|
| MK2069-01GITR | 功能描述:IC VCXO CLK SYNCHRONIZER 56TSSOP RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發生器，PLL，頻率合成器 系列:- 標準包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數:1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應商設備封裝:* 包裝:* |
| MK2069-03 | 制造商:ICS 制造商全稱:ICS 功能描述:VCXO-Based Clock Translator with High Multiplication |
| MK2069-03GI | 功能描述:IC VCXO CLK TRANSLATOR 56-TSSOP RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發生器，PLL，頻率合成器 系列:- 標準包裝:27 系列:Precision Edge® 類型:頻率合成器 PLL:是 輸入:PECL，晶體 輸出:PECL 電路數:1 比率 - 輸入:輸出:1:1 差分 - 輸入:輸出:無/是 頻率 - 最大:800MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 5.25 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:28-SOIC（0.295"，7.50mm 寬） 供應商設備封裝:28-SOIC 包裝:管件 |
| MK2069-03GITR | 功能描述:時鐘發生器及支持產品 VCXO-BASED CLOCK TRANSLATOR RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MK2069-04 | 制造商:ICS 制造商全稱:ICS 功能描述:VCXO-Based Universal Clock Translator |
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