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參數資料
| 型號： | MK2069-04GITR |
| 元件分類： | 時鐘產生/分配 |
| 英文描述： | 160 MHz, OTHER CLOCK GENERATOR, PDSO56 |
| 封裝： | 6.10 MM, 0.50 MM PITCH, TSSOP-56 |
| 文件頁數： | 1/19頁 |
| 文件大小： | 449K |
| 代理商： | MK2069-04GITR |
MK2069-04
MDS 2069-04 G
1
Revision 090905
Integr at ed Circuit Sy stems l 5 25 Race Street, San Jose, CA 9 512 6 l tel (40 8 ) 2 97-12 01 l
VCXO-Based Universal Clock Translator
Description
The MK2069-04 is a VCXO (Voltage Controlled Crystal
Oscillator) based clock generator that features a PLL
(Phase-Locked Loop) input reference divider and
feedback divider that have a wide numeric range
selectable by the user. This enables a complex PLL
multiplication ratio that can be used for translation
between clock frequency standards.
The on-chip VCXO produces a stable, low jitter output
clock using a phase detector frequency down to 8 kHz
or lower. This means the MK2069-04 can translate
between clock frequencies that have a low common
denominator, such as the 8 kHz frame clock common
with telecom standards. The MK2069-04 also provides
jitter attenuation of the input clock and can accept a low
input frequency as well.
The device is optimized for user configurability by
providing access to all major PLL divider functions. No
power-up programming is needed as configuration is
pin selected. External VCXO loop filter components
provide an additional level of user configurability.
The MK2069-04 includes a lock detector (LD) output
that serves as a clock status monitor. The clear (CLR)
input enables rapid synchronization to the phase of a
newly selected input clock.
Features
Input clock frequency <1 kHz to 170 MHz
Output clock frequency of 500 kHz to 160 MHz
Clock translation examples:
T1 (1.544 MHz) to/from E1 (2.048 MHz)
T3 (44.736 MHz) to/from E3 (34.368 MHz)
OC-3 (155.52 MHz) to/from T1 (1.544 MHz)
CCIR-601 (27 MHz) to/from SMPTE 274M
(74.125 MHz)
Jitter attenuation of input clock provided by VCXO
circuit. Jitter transfer characteristics user configured
through external loop filter component selection.
Low jitter and phase noise generation.
PLL lock status output
PLL Clear function allows seamless synchronizing to
an altered input clock phase
2nd PLL provides frequency translation of VCXO
PLL output (VCLK) to a higher or alternate output
frequency (TCLK).
Device will free-run in the absence of an input clock
based on VCXO frequency.
56-pin TSSOP package
Single 3.3 V power supply
5 V tolerant clock input
Available in Pb (lead) free package
Block Diagram
C h arge
Pum p
VC XO
P u lla b le
xtal
VC LK
X2
X1
ISET
4
VD D
4
CL R
LF
FV D iv ide r
1 to 40 96
RV
Div id e r
2 to 40 97
SV
Div id e r
1,2,12 ,1 6
IC L K
RV 1 1 :0
12
P has e
Detecto r
VC XO
PLL
FT D iv id e r
2 to 16, ev en o n ly
ST
Div id e r
2, 16
VC O
T ra n slato r
PL L
SV1 :0
2
F V 11:0
FT 2 :0
3
ST
TC L K
OE V
OE T
LD
OE L
GN D
RCL K
OE R
Loc k D e te c tor
12
LD R
LF R
RP V
Div id e r
1, 8
RP V
LD C
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