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參數資料
| 型號： | MM54C165 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Parallel-Load 8-Bit Shift Register |
| 中文描述： | 并聯負載8位移位寄存器 |
| 文件頁數： | 1/6頁 |
| 文件大小： | 135K |
| 代理商： | MM54C165 |
TL/F/5897
M
December 1992
MM54C165/MM74C165
Parallel-Load 8-Bit Shift Register
General Description
The MM54C165/MM74C165 functions as an 8-bit parallel-
load, serial shift register. Data is loaded into the register
independent of the state of the clock(s) when PARALLEL
LOAD (PL) is low. Shifting is inhibited as long as PL is low.
Data is sequentially shifted from complementary outputs, Q
7
and Q
7
, highest-order bit (P7) first. New serial data may be
entered via the SERIAL DATA (Ds) input. Serial shifting oc-
curs on the rising edge of CLOCK1 or CLOCK2. Clock in-
puts may be used separately or together for combined
clocking from independent sources. Either clock input may
be used also as an active-low clock enable. To prevent dou-
ble-clocking when a clock input is used as an enable, the
enable must be changed to a high level (disabled) only while
the clock is high.
Features
Y
Wide supply voltage range
3V to 15V
Y
Guaranteed noise margin
1V
Y
High noise immunity
0.45 V
CC
(typ.)
fan out of 2
driving 74L
Y
Low power TTL compatibility
Y
Parallel loading independent of clock
Y
Dual clock inputs
Y
Fully static operation
Connection and Block Diagrams
Dual-In-Line Package
TL/F/5897–1
Top View
TL/F/5897–2
Order Number MM54C165
*
or MM74C165
*
*
Please look into Section 8, Appendix D
for availability of various package types.
TL/F/5897–3
C
1995 National Semiconductor Corporation
RRD-B30M105/Printed in U. S. A.
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