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參數資料
| 型號： | MM54C175N |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 鎖存器 |
| 英文描述： | CMOS SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP16 |
| 封裝： | PLASTIC, DIP-16 |
| 文件頁數： | 1/6頁 |
| 文件大小： | 114K |
| 代理商： | MM54C175N |
TLF5900
MM54C175MM74C175
Quad
D
Flip-Flop
February 1988
MM54C175MM74C175 Quad D Flip-Flop
General Description
The MM54C175MM74C175 consists of four positive-edge
triggered D type flip-flops implemented with monolithic
CMOS technology Both are true and complemented out-
puts from each flip-flop are externally available All four flip-
flops are controlled by a common clock and a common
clear Information at the D inputs meeting the set-up time
requirements is transferred to the Q outputs on the positive-
going edge of the clock pulse The clearing operation en-
abled by a negative pulse at Clear input clears all four Q
outputs to logical ‘‘0’’ and Q’s to logical ‘‘1’’
All inputs are protected from static discharge by diode
clamps to VCC and GND
Features
Y
Wide supply voltage range
3V to 15V
Y
Guaranteed noise margin
10V
Y
High noise immunity
045 VCC (typ)
Y
Low power TTL compatibility
Fan out of 2
driving 74L
Connection Diagram
Truth Table
Dual-In-Line Package
TLF5900 – 1
Top View
Order Number MM54C175 or MM74C175
Each Flip-Flop
Inputs
Outputs
Clear
Clock
D
Q
LX
X
L
H
u
HH
L
H
u
LL
H
HH
X
NC
HL
X
NC
H e High level
L e Low level
X e Irrelevant
u e Transition from low to high level
NC e No change
C1995 National Semiconductor Corporation
RRD-B30M105Printed in U S A
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相關代理商/技術參數 |
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