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參數資料
型號: MM54C74J
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: 通用總線功能
英文描述: Dual D Flip-Flop
中文描述: CMOS SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, CDIP14
封裝: CERAMIC, DIP-14
文件頁數: 3/6頁
文件大小: 120K
代理商: MM54C74J
AC Electrical Characteristics
*
T
A
e
25
§
C, C
L
e
50 pF, unless otherwise noted
Symbol
Parameter
Conditions
Min
Typ
Max
Units
C
IN
Input Capacitance
Any Input (Note 2)
5.0
pF
t
pd
Propagation Delay Time to a
Logical ‘‘0’’ t
pd0
or Logical ‘‘1’’
t
pd1
from Clock to Q or Q
V
CC
e
5V
V
CC
e
10V
180
70
300
110
ns
ns
t
pd
Propagation Delay Time to a
Logical ‘‘0’’ from Preset or Clear
V
CC
e
5V
V
CC
e
10V
180
70
300
110
ns
ns
t
pd
Propagation Delay Time to a
Logical ‘‘1’’ from Preset or Clear
V
CC
e
5V
V
CC
e
10V
250
100
400
150
ns
ns
t
S0
, t
S1
Time Prior to Clock Pulse that
Data Must be Present t
SETUP
V
CC
e
5V
V
CC
e
10V
100
40
50
20
ns
ns
t
H0
, t
H1
Time after Clock Pulse that
Data Must be Held
V
CC
e
5V
V
CC
e
10V
b
20
b
8.0
0
0
ns
ns
t
PW1
Minimum Clock Pulse
Width (t
WL
e
t
WH
)
V
CC
e
5V
V
CC
e
10V
100
40
250
100
ns
ns
t
PW2
Minimum Preset and
Clear Pulse Width
V
CC
e
5V
V
CC
e
10V
100
40
160
70
ns
ns
t
r
, t
f
Maximum Clock Rise
and Fall Time
V
CC
e
5V
V
CC
e
10V
15.0
5.0
m
s
m
s
f
MAX
Maximum Clock Frequency
V
CC
e
5V
V
CC
e
10V
2.0
5.0
3.5
8.0
MHz
MHz
C
PD
*
AC Parameters are guaranteed by DC correlated testing.
Power Dissipation Capacitance
(Note 3)
40
pF
Note 1:
‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. Except for ‘‘Operating Temperature Range’’
they are not meant to imply that the devices should be operated at these limits. The table of ‘‘Electrical Characteristics’’ provides conditions for actual device
operation.
Note 2:
Capacitance is guaranteed by periodic testing.
Note 3:
C
PD
determines the no load AC power consumption of any CMOS device. For complete explanation see 54C/74C Family Characteristics Application
NoteDAN-90.
Switching Time Waveform
CMOS to CMOS
TL/F/5885–3
t
r
e
t
f
e
20 ns
3
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