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參數資料
| 型號： | MM54C86N |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 通用總線功能 |
| 英文描述： | Quad 2-Input EXCLUSIVE-OR Gate |
| 中文描述： | TTL/H/L SERIES, QUAD 2-INPUT XOR GATE, PDIP14 |
| 封裝： | DIP-14 |
| 文件頁數： | 1/4頁 |
| 文件大小： | 101K |
| 代理商： | MM54C86N |
TL/F/5887
M
February 1988
MM54C86/MM74C86 Quad 2-Input EXCLUSIVE-OR Gate
General Description
Employing complementary MOS (CMOS) transistors to
achieve wide power supply operating range, low power con-
sumption and high noise margin these gates provide basic
functions used in the implementation of digital integrated
circuit systems. The N- and P-channel enhancement mode
transistors provide a symmetrical circuit with output swing
essentially equal to the supply voltage. No DC power other
than that caused by leakage current is consumed during
static condition. All inputs are protected from damage due
to static discharge by diode clamps to V
CC
and GND.
Features
Y
Wide supply voltage range
3.0V to 15V
Y
Guaranteed noise margin
1.0V
Y
High noise immunity
0.45 V
CC
(typ.)
Fan out of 2
driving 74L
10 nW/package (typ.)
Y
Low power
TTL compatibility
Y
Low power consumption
Y
The MM54C86/MM74C86 follows the
MM54LS86/MM74LS86 Pinout
Connection Diagram
Dual-In-Line Package
TL/F/5887–1
Top View
Order Number MM54C86 or MM74C86
Truth Table
Inputs
Output
A
B
Y
L
L
H
H
L
H
L
H
L
H
H
L
H
e
High Level
L
e
Low Level
C
1995 National Semiconductor Corporation
RRD-B30M105/Printed in U. S. A.
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