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參數資料
| 型號： | MM54HC137J |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 通用總線功能 |
| 英文描述： | 3-to-8 Line Decoder With Address Latches (Inverted Output) |
| 中文描述： | HC/UH SERIES, OTHER DECODER/DRIVER, INVERTED OUTPUT, CDIP16 |
| 封裝： | CERAMIC, DIP-16 |
| 文件頁數： | 1/6頁 |
| 文件大小： | 131K |
| 代理商： | MM54HC137J |
TL/F/5310
M
D
November 1995
MM54HC137/MM74HC137 3-to-8 Line
Decoder With Address Latches
(Inverted Output)
General Description
This device utilizes advanced silicon-gate CMOS technolo-
gy, to implement a three-to-eight line decoder with latches
on the three address inputs. When GL goes from low to
high, the address present at the select inputs (A, B and C) is
stored in the latches. As long as GL remains high no ad-
dress changes will be recognized. Output enable controls,
G1 and G2, control the state of the outputs independently of
the select or latch-enable inputs. All of the outputs are high
unless G1 is high and G2 is low. The HC137 is ideally suited
for the implementation of glitch-free decoders in stored-ad-
dress applications in bus oriented systems.
The 54HC/74HC logic family is speed, function and pin-out
compatible with the standard 54LS/74LS logic family. All
inputs are protected from damage due to static discharge by
diodes to V
CC
and ground.
Features
Y
Typical propagation delay: 20 ns
Y
Wide supply range: 2–6V
Y
Latched inputs for easy interfacing.
Y
Fanout of 10 LS-TTL loads.
Connection and Functional Block Diagrams
Dual-In-Line Package
TL/F/5310–1
Order Number MM54HC137
or MM74HC137
TL/F/5310–2
C
1995 National Semiconductor Corporation
RRD-B30M115/Printed in U. S. A.
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